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A bang-bang phase detector for pam-n signaling

Abdekhoda, J ; Sharif University of Technology | 2023

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  1. Type of Document: Article
  2. DOI: 10.1109/ASICON58565.2023.10396104
  3. Publisher: IEEE Computer Society , 2023
  4. Abstract:
  5. Phase detector design for clock and data recovery (CDR) becomes challenging as the number of pulse amplitude modulation (PAM) levels increases. This paper presents a bang-bang phase detector (BBPD) architecture for PAM with N-level signaling (PAM-N) that balances the complexity and performance by utilizing an edge slicer whose threshold is adjusted according to the types of transitions. To accommodate high-speed applications, one-eight-rate architecture with carefully chosen timing is exploited. The validity of the proposed BBPD is examined for its PAM-4 and PAM-6 versions in 28 nm CMOS technology. © 2023 IEEE
  6. Keywords:
  7. Bang-Bang ; CDR ; Multi-mode ; NRZ ; PAM-4 ; PAM-6 ; PAM-N ; Phase Detector
  8. Source: Proceedings of International Conference on ASIC ; 2023 ; 21627541 (ISSN); 979-835031298-0 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/10396104