Loading...

A new scheme for low-power, low-latency, and interferer-tolerant wake-up receivers

Jafari Sharemi, H ; Sharif University of Technology | 2023

0 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/LSSC.2023.3325186
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2023
  4. Abstract:
  5. This letter presents a new approach to low-power, low-latency, and frequency-selective wake-up receivers. A novel architecture is introduced to achieve frequency domain selectivity, including analog techniques, that enable data detection without the need for power-hungry digital processing. A two-mode duty cycling is also utilized, which helps reduce the power consumption of the receiver significantly with negligible latency. A prototype of the proposed receiver is fabricated and verified in a 180-nm CMOS process. The fabricated chipset achieves a sensitivity of-84.9 dBm with 4.32-ms wake-up latency and drains an average current of 12.2 μ text A}. Interference tests show an outstanding signal-To-interference ratio (SIR) of-42/-49/-51 dB at 0.11%/0.22%/0.33% frequency offset from the carrier, confirming the interference immunity of the proposed design. © 2018 IEEE
  6. Keywords:
  7. Analog integrated circuits ; Interference suppression ; Low-latency communication ; Ultralow-power radio ; Wake-up radio ; Wireless sensor networks (WSNs)
  8. Source: IEEE Solid-State Circuits Letters ; Volume 6 , 2023 , Pages 285-288 ; 25739603 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/10287127