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Design of High Efficiency & Low Noise Integrated DC-DC Converter

Besharati Rad, Amir | 2024

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 57169 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Medi, Ali
  7. Abstract:
  8. In all electronic systems, the power management unit, as one of the main parts of the system, has the task of providing the necessary voltage for each sub-block of the system. Also, different blocks of electronic systems require different levels of supply voltage. In addition, the supply voltage level of the systems has increased due to the increase in the possibility of power transmission, and at the same time, there is a possibility of a drop in the supply voltage in battery-powered systems. Therefore, a DC-DC voltage converter that has a wide range of input and output voltage can increase the flexibility of the system. The design of DC-DC voltage converters whose output noise is at the level of linear regulators gives a great advantage to electronic systems due to the reduction of price, dimensions and losses. A wide-input/output-voltage-range buck converter with adaptive light-load efficiency improvement and seamlessmode transition for high-voltage applications is presented. The proposed design uses a load prediction structure to eliminate dc current sensor and to ensure high efficiency in the 0.02∼2-A load range. The pulsewidth modulation (PWM) mode has been used for near-full load. Since efficiency degradation at light loads occurs at different levels regarding the input and output voltage, a novel dynamic frequency pulsewidth modulation (DFPWM) with adaptive efficiency improvement mechanism is proposed, which activates efficiency improvement based on the input and output voltage at proper load current. Moreover, pulse frequencymodulation (PFM) has been used to guarantee high efficiency in a wider load range. The proposed trimode buck converter has seamless mode change. Input and output voltage ranges are 5∼30 V and 3∼15 V, respectively, which are compatible with automotive and RF applications. Output voltage disturbance is less than 60mVat 2-A load step with a 15-μs settling time for 30 to 3 V conversion. Moreover, output voltage disturbance in PWM/DFPWM and DFPWM/PFM mode change is zero and 60 mV, respectively. The proposed design has been implemented on 180-nm BCD technology with a 1.65 mm x 1.80 mm die size. An ultra-low-noise buck converter for noise-sensitive applications is presented, which utilizes a novel pseudo average current-mode control (ACMC) with an adaptive ramp generator to decrease the baseband noise. Also, in order to suppress electromagnetic interference (EMI) and high-frequency spurs, spread spectrum and secondary filter are used, respectively. The proposed ACMC buck converter suppresses the switching frequency perturbation effect on the output voltage, and as a result in the spread spectrum condition, only a small amount of noise is added to the output voltage in the baseband frequency. For the spread spectrum with an external clock, a phase-locked loop is used,which synchronizes the internal oscillator and adapts the ramp generator slope to suppress spread spectrum baseband noise. The proposed ACMC converter achieves only 58 μVrms noise in 100 Hz–100 kHz frequency range. Also, a ±10% random spread spectrum architecture suppresses the EMI level by 11 dB while achieving only 88 μVrms and 156 μVrms noise for internal and external clock synchronization, respectively. The peak efficiency of the converter is 95% and the output voltage disturbance is 100 mV at a 2-A load step with 16 μs settling time. The proposed design is implemented on a 180-nm BCD technology occupying a 1.65 mm x 3.70 mm die size
  9. Keywords:
  10. Multi Output DC-DC Converter ; Power Management ; Buck Converter Design ; Low Noise ; High Efficiency ; Pulse Width Modulation (PWM) ; Electromagnetic Interference (EMI)

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