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Blenda: dynamically-reconfigurable stacked DRAM

Bakhshalipour, M | 2024

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  1. Type of Document: Article
  2. DOI: 10.1109/MICRO61859.2024.00098
  3. Publisher: IEEE , 2024
  4. Abstract:
  5. This paper proposes Blenda, a dynamically-partitioned memory-cache blend architecture for giga-scale die-stacked DRAMs. Blenda architects the stacked DRAM partly as memory and partly as cache, and dynamically adjusts each part's size to workloads' demands. The memory part hosts hot data objects and serves requests to them efficiently (i.e., without metadata overheads). The cache part captures transient data and filters requests to bandwidth-limited off-chip DRAM. Blenda provides three key contributions: (i) Blenda partitions stacked DRAM's capacity in a workload-aware manner: different workloads enjoy different memory-cache configurations. (ii) Blenda is reactive: the configuration is adjusted to workloads' phases dynamically and application-transparently: no reboot or user involvement are needed. (iii) Blenda gracefully transitions among configurations: no data invalidation is required upon most reconfigurations. We simulate 15 diverse big-data workloads running on a state-of-the-art processor and show that Blenda outperforms the best-performing prior architecture by 34%. Blenda's total storage overhead is less than 100 bytes per core. © 2024 IEEE
  6. Keywords:
  7. 3D Integration ; Die-Stacked DRAM ; DRAM Cache ; HBM ; Hybrid Memory Systems ; In-Package DRAM ; Cache memory ; Memory architecture ; Reconfigurable architectures
  8. Source: Proceedings of the Annual International Symposium on Microarchitecture, MICRO ; 2024 , Pages 1323-1337 ; 10724451 (ISSN); 979-835035057-9 (ISBN)
  9. URL: https://www.computer.org/csdl/csdl/proceedings-article/micro/2024/505700b323/22nixKU2NGw