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Systematic VLSI Design for Digital Hearing Assist Device

Emami Varzeghani, Pooya | 2024

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 58057 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Haj Sadeghi, Khosrow
  7. Abstract:
  8. According to the World Health Organization, 466 million people (over 5 percent of the world's population) suffer from hearing impairments. A digital hearing aid device consists of analog processing units and digital signal processing blocks along with analog-to-digital and digital-to-analog converters. The input audio signal captured by the microphone is fed to an analog-to-digital converter. The digital output is processed by the digital signal processor, and the processed signal is then converted back to an analog signal by the digital-to-analog converter. This is the general structure of a hearing aid device, designed to improve the quality of the input signal, increase the hearing threshold of the hearing-impaired individual at frequencies they have trouble hearing, and enhance environmental effects and the input signal volume. Furthermore, the World Health Organization highlights that a large portion of the low and middle-income population cannot afford hearing aids suitable for their hearing levels. The reasons include high manufacturing costs, unsuitable device structures for mass production at low costs, and similar issues. Among the challenges that designers face in creating suitable hearing aids that meet implementation limitations are the silicon area consumption, energy consumption which depends on the chip's power consumption, the quality of the output signal, and the physical structure of the hearing aid device. These factors always challenge hardware designers. Various architectures have been proposed and implemented for hearing aid devices, each with its advantages and disadvantages, depending solely on the manufacturer's requirements and similar considerations. The overall structure of the hearing aid device incorporates methods and algorithms such as synthesis and analysis filter banks, noise reduction blocks, dynamic range compression, and feedback cancellation from the input signal, as well as beamforming and localization algorithms. In this thesis, we aim to design a hearing aid device that meets the necessary requirements of individuals with hearing impairments while also reducing critical factors such as chip silicon area, device power consumption, and providing suitable sound quality considering the needs of the users. Finally, the implemented device has been synthesized and implemented in 65nm technology, and its results have been compared with similar works. According to the implementation results, we have managed to reduce the silicon area and power consumption by 70% and 10%, respectively, compared to one of the similar works. Additionally, this device has been implemented entirely in hardware, unlike previous works that required the use of instruction processors for processing operations. This reduces the manufacturing cost of the device
  9. Keywords:
  10. Digital Signal Processing ; Very Large Scale Integration (VLSI)Circuits ; Systematic Design ; Accelerators ; Digital Hearing Assist ; Accelerator Blocks

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