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Design of Low Power Harmonic Rejection Mixer for Wideband Application

Jafarpour Dahaghani, Reza | 2025

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 58317 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Akbar, Fatemeh
  7. Abstract:
  8. The increasing demand for communication bandwidth and limited spectrum availability have heightened the complexity of radio front-end circuits in IoT applications. Achieving spectral efficiency is a key challenge, particularly for IoT devices operating at specific frequency bands such as 315 MHz, 433 MHz, 868 MHz, and 915 MHz.Due to the limited linearity of the transmit path, harmonic distortion components, known as counter intermodulation (CIM) products, are generated. These CIM products can directly fall into the receiver (RX) band or enter it via cross-modulation, thereby degrading the frequency division performance. Additionally, CIM products can interfere with protected bands, violating spectral emission requirements. Recently, CIM products particularly counter 3rd-order intermodulation products (CIM3) caused by the 3rd-order nonlinearity of the transmit path have been identified as a critical design parameter for IoT applications. A major contributor to CIM arises from the intermodulation between the desired signal and the 3rd-order harmonic component of the local oscillator (LO) signal. In this work, a novel harmonic rejection mixer (HRM) architecture is proposed, which achieves optimal performance across the desired bandwidth in terms of harmonic rejection ratio (HRR) and linearity while significantly reducing power consumption. In this design, switching signals with phases of 0° and 90° are combined using a switched-capacitor circuit and applied to a double-balanced NMOS mixer stage. Additionally, a switching signal with a 45° phase is separately applied to a double-balanced PMOS mixer stage. By integrating these two mixer stages in a current-reuse configuration and applying a weighting ratio of 1:√2, a new HRM architecture is realized. This architecture improves power consumption, output swing, and impedance characteristics. The HRM prototype was implemented using the GlobalFoundries (GF) RF CMOS 180 nm process. The layout core occupies an area of 0.086 mm2, including the switched-capacitor and biasing circuits. The operating frequency ranges from 50 MHz to 915 MHz. Measurement results show that the proposed HRM achieves a conversion gain ranging from 9.25 dB to 13 dB across the operating frequency range. The output 1 dB compression point (P1dB) is measured at -7.6 dBm, and the input 3rd-order intercept point (IIP3) is 4.58 dBm at a frequency of 433 MHz. The measured HRR3 exceeds 25 dB, while the HRR5 surpasses 27 dB over the entire operating frequency range. The HRM consumes only 524 µW of power with a supply voltage of 1.8 V
  9. Keywords:
  10. Bandwidth ; Harmonic Rejection ; Low Noise ; Ultra Wideband ; Low Power Consumption ; Low Power Mixers

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