Sharif Digital Repository

In this paper an integrated core, high reliability, linear-rotational resolver with a simple slotless configuration is proposed. The moving part of the proposed resolver has only one helical winding. While, its stator needs at least two individual windings to be able to determine the linear and angular position in simultaneous linear and rotational, helical, motions. Three different configurations are proposed for the stator's windings: (1) helical and horizontally skewed winding (2) helical and vertically skewed winding (3) horizontally and vertically skewed windings. The influence of the mentioned configurations is discussed in the terms of sensor's accuracy in independent and simultaneous... 

Two-degree-of-freedom (2-DOF) electrical machines require position sensors for their motion control. In comparison with using two independent sensors, using a 2-DOF sensor enhances the closed-loop control system's performance. However, due to the 3-D structure of the 2-DOF sensor, its performance evaluation needs 3-D analysis. Also, due to helical motion the accuracy deterioration of the sensor, under mechanical faults needs more attention. Although the finite element method (FEM) is the best way to simulate such sensors, most of the commercial packages for transient finite element simulations are not able to consider two separate motions simultaneously. Furthermore, FEM has a high... 

Darrieus type vertical axis wind turbines have several advantages over other wind turbines for local electricity generation in urban environments. However, the main aerodynamic challenge is the negative impacts of the dynamic stall phenomenon on the turbine performance. This study numerically scrutinizes the effects of plasma actuators on the dynamic stall control and performance improvement of a Darrieus turbine. For this sake, unsteady Reynolds-averaged Navier-Stokes equations are solved using a pressure-based finite volume method. The Suzen-Hoang plasma actuator model is employed to calculate the body forces attributed to the plasma actuator. First, the dynamic stall characteristics of... 

Using multiple position sensors in the control system of Two-Degrees of Freedom (2-DOF) motors causes it more complicated than that of conventional 1-DOF ones. However, employing a 2-DOF position sensor in comparison with two independent sensors, reduces the complexity, mass and volume of the system. The common 2-DOF sensors are able to determine the position in linear, rotational, and helical motion. Yet, they suffer from accuracy reduction due to the longitudinal end effect. Therefore, analytical modelling and the relevant compensation methods are discussed. The accuracy of the model is approved by comparing its results with those of 3D time transient finite element method. Afterwards, the... 

For every h ∈ ℕ, a graph G with the vertex set V (G) and the edge set E(G) is said to be h-magic if there exists a labeling l: E(G) → ℤh{0} such that the induced vertex labeling s: V (G) → ℤh, defined by s(v) = Puv∈E(G) l(uv) is a constant map. When this constant is zero, we say that G admits a zero-sum h-magic labeling. The null set of a graph G, denoted by N(G), is the set of all natural numbers h ∈ ℕ such that G admits a zero-sum h-magic labeling. In 2012, the null sets of 3-regular graphs were determined. In this paper we show that if G is an r-regular graph, then for even r (r > 2), N(G) = ℕ and for odd r (r ≠ 5), ℕ {2, 4} ⊆ N(G). Moreover, we prove that if r is odd and G is a 2-edge... 

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are... 

Latency-insensitive design (LID) is a correct by-construction methodology for system on chip design that prevents multiple iterations in synchronous system design. However, one problem in the LID is system throughput reduction. In this study, a protocol is proposed to increase the throughput of internal cores in the latency-insensitive systems when there are several repetitive structures. The validation of the protocol is checked for latency equivalency in various system graphs. A shell wrapper to implement the protocol is described and superimposed logic gates for the shell wrapper are formulated. Simulation is performed for 12 randomly generated systems and four actual systems. The... 

Let G be a graph and H be an abelian group. For every subset SH a map φ:E(G)→S is called an S-flow. For a given S-flow of G, and every v∈V(G), define s(v)=∑uv∈E(G)φ(uv). Let k∈H. We say that a graph G admits a k-sum S-flow if there is an S-flow such that for each vertex v,s(v)=k. We prove that if G is a connected bipartite graph with two parts X={x1,⋯,xr}, Y={y1,⋯, ys} and c1,⋯,cr,d1,⋯, ds are real numbers, then there is an R-flow such that s( xi)=ci and s(yj)=dj, for 1≤i≤r,1≤j≤s if and only if ∑i=1rci=∑j=1s dj. Also, it is shown that if G is a connected non-bipartite graph and c1,⋯,cn are arbitrary integers, then there is a Z-flow such that s(vi)=ci, for i=1, ⋯,n if and only if the number... 

Communication wire delay between multiple blocks is becoming a critical issue in System on Chip (SoC) design. Scheduling-based Latency-Insensitive Design (LID) is a method to alleviate wire delays by utilizing a central scheduling scheme for periodic clock gating of the blocks. The scheduling scheme resides in shift registers as sequences of '1' and '0' bits. In many systems, these sequences are too long, and have large area overhead. This problem indisposes the implementation of the scheduling based protocol. This paper proposes an algorithm that finds sequences with shorter lengths in comparison with the prior algorithm. On synthetic/random test cases, the algorithm gives 45% reduction on... 

Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm...