Sharif Digital Repository

Heterogeneity is one of the challenges in the current NoC (Network-on-Chip) domain which oblige designers to consider less regular topologies to provide the best cost-performance trade-off while minimizing resource and power consumption and providing the maximum flexibility. Irregular mesh is a topology which combines the benefits of regularity and advantage of irregularity. Another important issue in any NoC is the selection of routing algorithm which provides the best performance. Routing algorithms especially those coupled with wormhole switching should deal with deadlock occurrences. Deadlock detection and recovery-based routing schemes for this type of switching gained attraction since... 

Resource sharing is the most important feature of a Grid. Resource discovery enables users to find the most suitable resources to run Grid jobs on. Resource discovery systems are often centralized or hierarchical. These structures are usually prone to a single point of failure, and unbalanced distribution of processing and storage load, making them inefficient as the Grid grows. These challenges have led researchers to adapt distributed approaches, such as Peer-to-Peer file sharing solutions. The important differences between Grid resource discovery and P2P file discovery (e.g. different resource attributes, queries, change patterns etc.) make it difficult to port the existing solutions to... 

The increasing complexity of integrated circuits drives the research of new on chip interconnection architectures. Network On Chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Different routing algorithms have been proposed for NoCs such as XY deterministic algorithm, and WF (West First), NL (North Last) and NF (Negative First) as partially adaptive algorithms. OE (Odd Even) is not based on adding virtual channels to network topologies. Unlike previous methods, which rely on prohibiting certain turns in order to achieve... 

Multicasting has gained a lot of research attentions in facilitating group communications in wireless networks. Applying multicast mechanisms in Wireless Mesh Networks, brings a lot of benefits to these networks. In our research, we have introduced Cost-aware On-Demand Multicast Routing Protocol (C-ODMRP) as an extension of ODMRP that supports QoS provisioning for high quality applications in WMNs. In C-ODMRP, the nodes are prevented from applying the links that do not meet the QoS requirements. The multicast receivers are provided with resource-aware information to efficiently compute the cost of the routes when multiple routes from source to destination nodes are established. C-ODMRP takes... 

Network-on-Chip (NoC) is a promising on-chip communication paradigm which targets the scalability and predictability problems of the traditional on-chip mechanisms. However, it has been shown that, in future technologies (especially 22 nm technology), the power consumption of the current NoCs is about 10 times higher than the power budget can be devoted to them. Application-specific optimization is one of the most effective approaches to bridge the exiting gap between the current and the ideal NoC power consumptions. However, almost all existing application-specific customization methods try to customize NoCs for... 

Studying data flows in conventional applications of Multi-Processor System-on-Chips (MPSoCs) denotes that most of these flows are the ones that transfer huge volume of data in inter-core communications. Previous works try to present architecture for interconnection network which some paths with low power and latency are reserved (statically or dynamically). However all of the presented methods are based on subnetworks or mechanism of transferring control messages (to establish a path and tear it down after transmission of data). Optical connections with low cost, low power and high bandwidth are good candidates to reduce power consumption of Network-on-Chips (NoCs). Therefore, using optical... 

Delay Tolerant Networks are a variation of Mobile Ad Hoc Networks, in which low density of nodes in the network area results in global disconnectivity among the nodes. In these networks, communication of data throughout the networks takes place by the means of mobility; nodes store data packets and carry them around the network and forward them to other nodes they encounter along the way. In these situations, a proper selection of data to be exchanged between nodes has a great impact on the quality of data distribution in the whole networks. There is a common assumption among most of the techniques presented in category of Delay Tolerant Networks. They assume the probability of more than two... 

Emerging memory technologies such as STT-RAM, PCM and resistive RAM are probable technologies for caches and main memories of the future multi-core architectures. This is because of their high density, low leakage current and non-volatility. Nevertheless, the overhead of latency and energy consumption of write operation in these technologies are the main open problems. Previous works have suggested various solutions, in architecture and circuit levels, to reduce the writing overheads. In this research, we study the integration of STT-RAM in 3-dimensional multi-core environments; and propose solutions to address the problem of writing overheads when using this technology in cache... 

Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. This concept is the basis of the Dark Silicon definition. To address this issue, it is needed a structure to guaranty Limited power budget and obtain sufficient flexibility and performance for different applications with variety communication needs. Regarding to this structure, our aim is to present a platform for Networks-on-Chip that uses clustering and resource sharing among cores. Moreover, as task mapping on processing elements in NOCs is one of the most effective way to... 

As technology shrinks, the static power consumption is getting worse. Moreover, considering high usage of General-Purpose Graphics Processing Units (GPGPU), reducing the static power of GPGPUs is becoming an important issue. Execution units in GPGPUs are one of the most power hungry units that play an essential role in total power consumption of GPGPUs. On the other hand power gating is a promising method to reduce static power consumption. In this project, we propose a novel method to implement power-gating method for execution units with the negligible performance and power overheads. We utilize out of order execution in intra warp to keep the power-gated resources in off state more than... 

Memories today expose an all-or-nothing correctness model thatincurs significant costs in performance, energy, area, and designcomplexity. But not all applications need high-precision storagefor all of their data structures all of the time. This these proposesmechan-isms that enable applications to store data approximately in a phase change memory main memoryand shows that doing so can improve the performance and reduce the power consumption by proposing two mechanisms. The First allows errors in multi-level cells by reducing the number ofprogramming pulses used to write them. The second mechanism reduces the number of error-prone patterns in the content of data block through a lightweith... 

As a promising replacement for the conventional high-latency and low-throughput HDDs, NAND Flash-based solid state drives have been increasingly used in data center and cloud applications as well as high-end enterprise servers. However, capacity scaling is a controversial challenge of the SSD manufacturers to keep pace with the competitors in the storage market. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of Flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-Flash standards to respond to ever increasing... 

Dynamic Random Access Memory (DRAM) has been the leading main memory technology during the last four decades. In deep sub-micron regime, however, scaling DRAM comes with several challenges caused by charge leakage and imprecise charge placement. Phase Change Memory (PCM) technology is known as one of the most promising technologies to replace DRAM. Compared to competitive non-volatile memories, PCM benefits from best attributes of fast random access, negligible leakage energy, superior scalability, high density, and operating in both Single-level Cell (SLC) and Multi-level Cell (MLC) storage levels without imposing large storage overhead. Unfortunately, density advantage of MLC PCM devices... 

Appearance of CUDA architecture results in GPU introduction as a suitable platform for parallel processing. Massive usage of GPGPUs in various applications forces the manufacturers to produce this processor with different configurations based on their application demands. But always the design approach observes a ratio between processing capability and bandwidth of GPGPUs. In this way mostly in all GPGPU series the bandwidth increases with growth of GPGPU processing power. At first glance this ratio seems reasonable because more process needs more data. However this approach does not pay attention to the behavior of a wide range of workloads which do not need such a bandwidth. Mentioned... 

In this project we present a method to support execution of multiple applications on an NoC simultaneously. To this end we are going to use resource sharing methods, especially Spacial Division Multiplexing (SDM). In this work we first present a mapping algorithm to map the nodes of a compound graph (a graph that is composed of all the task graphs that are supposed to work simultaneously) in to mesh nodes. We also present an architecture to support SDM. After that we present a routing and resource allocation algorithm to find a circuit for each communication flow in the task graph. Our results show that the proposed mapping algorithm reduces the average packet latency compared to NMAP... 

Project in brief: reconfiguring the network according to application which has been run on the network is one of the ways to improve using resources in the network-on-chip. There is a hierarchical cluster based NOC. In this network, nodes are going to partition into clusters. Every cluster’s node can have its own configuration and the configuration of inside of each cluster is unchangeable however the relationship between clusters is configurable. This ability is made by some switches which are located between clusters and they can change the way that clusters are related. The number of nodes which is inside the cluster are cluster size and the number of switches between two adjacent... 

The shrinkage of feature sizes has resulted in global wiring delays being the bottleneck in on-chip interconnects. As a consequence, Network-on-Chip (NoC) emerged as a desirable interconnect structure between Processing Elements (PEs) on a chip. On the other hand, due to the non-uniform communication patterns among PEs, it is beneficial for the routers input ports to have a reconfigurable buffer structure. Having this in mind, we proposed a reconfigurable microarchitecture for on-chip routers which is able to reconfigure the Virtual Channels (VCs) in input ports, without lowering the clock frequency of the router. For this purpose, we presented a simple and efficient mechanism for monitoring... 

Motivated by the fact of lack of infra-structure in multi-hop wireless networks, there is a controversial issue of assurance in protocols execution. Due to dynamic structure of these networks, local information should be considered for implementing related algorithms implementation. Selecting logical neighbors, named topology control, is one of these algorithms which have to take sanctity of the execution into consideration. To cope with these issues it can be beneficial to explore algorithm design problem in view of independent and rational agents. In other words, in investigating topology control algorithms in the presence of independent nodes, several contradictory problems were observed... 

Efficient processor allocation and job scheduling algorithms are critical if the full computational power of large-scale multicomputers is to be harnessed effectively. Processor allocation is responsible for selecting the set of processors on which parallel jobs are executed, whereas job scheduling is responsible for determining the order in which the jobs are executed. Many processor allocation strategies have been devised for mesh-connected multicomputers and these can be divided into two main categories: contiguous and non-contiguous. In contiguous allocation, jobs are allocated distinct contiguous processor submeshes for the duration of their execution. Such a strategy could lead to high... 

The use of raed cache of hard disk or solid state drives has a magnificent effect on their performance, power consumption, and their endurance. However, one of the main problems of their read cache is its low hit ratio. Thus, the read cache must be used more efficiently. Based on previous studies, nearly all of the blocks which are brought to the read cache are zero-reuse or dead-on-arrival, which means that after the blocks enter to the read cache, they are not accessed until they are evicted. Thus, a large portion of the disk read cache is nearly unused because of these dead blocks. In this thesis, we will design a disk read cache which does not allow to the dead blocks to enter the...