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A Scalable and High-performance Design Architecture for SSD

Tavakkol, Arash | 2015

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 48001 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. As a promising replacement for the conventional high-latency and low-throughput HDDs, NAND Flash-based solid state drives have been increasingly used in data center and cloud applications as well as high-end enterprise servers. However, capacity scaling is a controversial challenge of the SSD manufacturers to keep pace with the competitors in the storage market. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of Flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-Flash standards to respond to ever increasing application demands. In the current study, we first give a deep look at how different Flash parameters and SSD internal designs affect the actual performance and scalability of the conventional architecture. Our experiments show that SSD performance improvement through either enhancing intra-chip parallelism or increasing the number of Flash units is limited by frequent contentions occurred on the shared channels. Our discussion will be followed up by presenting and evaluating Network-on-SSD (NoSSD), an architectural technique that leverages pipeline and parallel properties of network routers to direct access requests of a Flash chip in parallel with others. NoSSD properties, such as router architectur, packet injection policy, and packet prioritization policy, are tuned and customized according to the communication requirements of SSD internal traffic. Our solution helps improving SSD functionality through sufficiently supporting operation interleaving and facilitates capacity scaling through increasing the number of Flash-chips. In fact, Flash chips can be added with much less concerns on board-level signal integrity challenges including channels' maximum capacitive load, output drivers' slew rate, and impedance control. NoSSD can further help to exploit different levels of SSD internal parallelism. In conventional desings, the SSD controller firmware is designed to reduce contention probability over bus channels. However, the shared and distributed nature of NoSSD facilitates the efficient use of communication resources for inter-Flash communication. Therefore, we propose novel management algorithms and policies of the SSD controller firmware that more concentrate on exploiting intra-Flash chip parallelism levels. The evaluation results show that the proposed algorithms substantially improve the usage of intra-Flash parallelisms. Moreover, the proposed policies for long-term usage and recycling of Flash blocks, considerably reduce the negative side-effects of garbage collection execution on parallel execution of I/O oeprations. Hence, the exploitation of intra-Flash parallelism levels will be stable during the SSD lifetime
  9. Keywords:
  10. Garbage Collection ; Solid State Disk Drive ; Flash Memory ; Flash Translation Layer (FTL) ; Network-based Communication ; Address Mapping

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