Sharif Digital Repository

With current memory scalability challenges, Phase Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that is highly affected by pro-cess variation in nanometer regime. This increases the vari- ation in cell lifetime resulting in early and sudden reduc- tion in main memory capacity due to wear-out of few cells. When some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redi- rection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. On contrary, we... 

With current memory scalability challenges, Phase Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that is highly affected by pro-cess variation in nanometer regime. This increases the vari- ation in cell lifetime resulting in early and sudden reduc- tion in main memory capacity due to wear-out of few cells. When some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redi- rection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. On contrary, we... 

Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors. Previous studies have focused on either presenting various cache architectures/management techniques to improve the lifetime of STT-RAM caches or utilizing different Error Correcting Codes (ECCs) to protect against the permanent and transient errors. However, there is no quantitative analysis in the literature to determine the impact of ECCs on the lifetime of the STT-RAM caches. This paper formulates this impact... 

Purpose: Presence of photon attenuation severely challenges quantitative accuracy in single-photon emission computed tomography (SPECT) imaging. Subsequently, various attenuation correction methods have been developed to compensate for this degradation. The present study aims to implement an attenuation correction method and then to evaluate quantification accuracy of attenuation correction in small-animal SPECT imaging. Methods: Images were reconstructed using an iterative reconstruction method based on the maximum-likelihood expectation maximization (MLEM) algorithm including resolution recovery. This was implemented in our designed dedicated small-animal SPECT (HiReSPECT) system. For... 

This study examined Iranian EFL learners’ preferences regarding oral Corrective Feedback (CF) in a TOEFL speaking course. A 30-item questionnaire was administered to 32 participants in a TOEFL preparation course to elicit EFL learners’ views concerning their CF expectations. The results showed that based on the nature and objective of the course, students cared about their accuracy while fluency for these students was of secondary importance. Therefore, CF was regarded as crucial and necessary by the participants and they considered their grammatical errors as the most important one to be corrected followed by vocabulary and pronunciation errors. In terms of CF type, explicit and delayed... 

In this paper, we present the most general form for error control coding using finite field multi-rate filters. This method shows how different types of codes can easily be generated by multi-rate filters and filter banks. In all previous works, codes and syndromes were generated using prefilters. Here we present simple multi-rate structures for encoding and generating syndrome. We show that all kinds of arbitrary rate K/L, circulant linear codes can be generated by these structures. Then we claim that a similar simple structure for syndrome generation in all presented cases exist  

A general construction for deletion/insertion correcting codes is proposed by concatenating codes derived from a heuristic maximal independent set algorithm on an appropriately defined graph. Our heuristic algorithm is polynomial with respect to the number of nodes in the graph. This methodology may be used for construction of any length n, s-deletion code. Our experimental results show that cardinalities of our codebooks exceed sizes of all previously known constructions. In fact, they are comparable to Levenshteins lower bound  

FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any... 

Data integrity of words coming out of the caches needs to be checked to assure their correctness. This paper proposes a cache placement scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without compromising performance and area with respect to the similar one, fully associative cache. The results obtained from simulating some standard... 

Scratchpad memory (SPM) is widely used in modern embedded processors to overcome the limitations of cache memory. The high vulnerability of SPM to soft errors, however, limits its usage in safety-critical applications. This paper proposes an efficient fault-tolerant scheme, called cache-assisted duplicated SPM (CADS), to protect SPM against soft errors. The main aim of CADS is to utilize cache memory to provide a replica for SPM lines. Using cache memory, CADS is able to guarantee a full duplication of all SPM lines. We also further enhance the proposed scheme by presenting buffered CADS (BCADS) that significantly improves the CADS energy efficiency. BCADS is compared with two well-known... 

Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and... 

Self-oscillating converters operating in the critical conduction mode are popular in low power applications because of their simplicity and low cost. However, these converters are not suited for Power Factor Correction (PFC) because the peak switch current is controlled to regulate the output voltage and does not follow the shape of the line voltage waveform. A new control circuit implementation is proposed for a self-oscillating boost converter to achieve power factor correction. A full featured design example is provided which can be simplified for use in various cost sensitive applications such as electronic lighting, etc. This wide input voltage range self-oscillating PFC prototype... 

In this study, a simple and novel control technique for Power Factor Correction (PFC) is introduced, which is a SEPIC-based (Single-ended Primary-inductor Converter based) rectifier with high input power factor. Operation of the proposed method is based on sampling of input and output voltages in SEPIC rectifier. Using samples of input and output voltage, this control system makes the input current to follow a sinusoidal path. As a result, the line current?'s Total Harmonic Distortion (THD) is reduced and the input power factor is improved. This paper also compares the new method with the conventional control method for the power factor correction. In order to examine the proposed control... 

A novel control strategy based on predictive control is presented for continuous conduction mode boost converter which operates as a power factor correction. In the proposed algorithm two horizons for the behavior of the circuit are predicted which improves the total harmonic distortion, mainly the low frequency harmonics. The algorithm doesn't need elaborating calculations therefore, implementation of the controller using low price processor is feasible. Moreover, an extra horizon of the prediction leads to expansion of the calculation time. Reduction of the harmonic distortion of the input current and improvement of the power factor have been demonstrated on an isolated boost PFC converter... 

Absolutely maximally entangled (AME) states are pure multi-partite generalizations of the bipartite maximally entangled states with the property that all reduced states of at most half the system size are in the maximally mixed state. AME states are of interest for multipartite teleportation and quantum secret sharing and have recently found new applications in the context of high-energy physics in toy models realizing the AdS/CFT-correspondence. We work out in detail the connection between AME states of minimal support and classical maximum distance separable (MDS) error correcting codes and, in particular, provide explicit closed form expressions for AME states of n parties with local... 

Spin-Transfer Torque Magnetic RAM (STT-MRAM) as one of the most promising replacements for SRAMs in on-chip cache memories benefits from higher density and scalability, near-zero leakage power, and non-volatility, but its reliability is threatened by high read disturbance error rate. Error-Correcting Codes (ECCs) are conventionally suggested to overcome the read disturbance errors in STT-MRAM caches. By employing aggressive ECCs and checking out a cache block on every read access, a high level of cache reliability is achieved. However, to minimize the cache access time in modern processors, all blocks in the target cache set are simultaneously read in parallel for tags comparison operation... 

In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008  

The interaction of the sub-picosecond UV laser in sub-relativistic intensities with deuterium is investigated. At high plasma temperatures, based on the quantum correction in the collision frequency, the electron heating and the ion block generation in plasma are studied. It is found that due to the quantum correction, the electron heating increases considerably and the electron temperature uniformly reaches up to the maximum value of 4.91-×-107-K. Considering the quantum correction, the electron temperature at the laser initial coupling stage is improved more than 66.55% of the amount achieved in the classical model. As a consequence, by the modified collision frequency, the ion block is...