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    Fault Tolerance in Cloud Storage Systems Using Erasure Codes

    , M.Sc. Thesis Sharif University of Technology Safaei, Bardia (Author) ; Miremadi, Ghassem (Supervisor)
    Abstract
    International Data Company (IDC) has reported, at the end of 2020, the total amount of digital data stored in the entire world will reach 40 thousand Exabytes. The idea of accessing this volume of data, anywhere at any time by exploiting commodity hardware, led into the introduction of cloud storage. The abounded rate and variety of failures in the equipment used in cloud storage systems, placed fault tolerance, at top of the challenges in these systems. HDFS layer in Hadoop has provided cloud with reliable storage. Replication is the conventional method to protect data against failures in HDFS. But the storage overhead is a big deal and therefore designers are tending towards erasure codes.... 

    Viterbi Decoder Implementation on GPGPU

    , M.Sc. Thesis Sharif University of Technology Mohammadidoost, Alireza (Author) ; Hashemi, Matin (Supervisor)
    Abstract
    In this project, a method is emoloyed to implement a Viterbi decoder on GPGPU. This method is based on combining all steps of the algorithm. This combination has some challenges that are related to differences between different steps of the algorithm. So in this project, some solutions are found to handle these challenges and a high-throughput Viterbi decoder is acheived  

    Designing a 32-Bit Fault-Tolerant ALU Using EDAC

    , M.Sc. Thesis Sharif University of Technology (Author) ; Vosughi Vahdat, Bijan (Supervisor) ; Mortazavi, Mohammad (Supervisor)
    Abstract

    Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since... 

    Brain Decoding Across Subjects

    , M.Sc. Thesis Sharif University of Technology Nasiri Ghosheh Bolagh, Samaneh (Author) ; Shamsollahi, Mohammad Bagher (Supervisor)
    Abstract
    In recent years, techniques in articial intelligence have become an important tool in the analysis of physiological signals. While the application of machine learning techniques has proved useful in other elds, researchers have had difficulty proving its utility for the analysis of physiological signals. A major challenge in applying such techniques to the analysis of physiological signals is dealing effectively with inter-patient differences. The morphology and interpretation of physiological signals can vary dep ending on the patient. This poses a problem, since statistical learning techniques aim to estimate the underlying system that produced the data. If the system (or patient) changes... 

    Application of Artificial Intelligence for Encoding and Decoding in the Internet of Things Communication

    , M.Sc. Thesis Sharif University of Technology Hassanpour, Mohammad Amin (Author) ; Farhadi, Alireza (Supervisor)
    Abstract
    One of the important issues in the field of telecommunications is the optimization of coding algorithms. Especially, in the field of the Internet of Things (IoT) due to the low processing power and the limitation in the energy storage of devices, the needs for such optimized algorithms are more essential. One effective method to improve coding algorithms in the transmission of messages is obtained by paying more attention to the amount of information contained in each part of the message and transmit information accordingly. Some coding methods have addressed this issue indirectly, but they do not pay enough attention to this practical issue. Based on the simple but practical idea mentioned... 

    Blind image watermarking based onsample rotation with optimal detector

    , Article European Signal Processing Conference, 24 August 2009 through 28 August 2009, Glasgow ; 2009 , Pages 278-282 ; 22195491 (ISSN) Sahraeian, S. M. E ; Akhaee, M. A ; Marvasti, F ; Sharif University of Technology
    Abstract
    This paper present a simple watermarking approach based on the rotation of low frequency components of image blocks. The rotation process is performed with less distortion by projection of the samples on specific lines according to message bit. To have optimal detection Maximum Likelihood criteria has been used. Thus, by computing the distribution of rotated noisy samples the optimum decoder is presented and its performance is analytically investigated. The privilege of this proposed algorithm is its inherent robustness against gain attack as well as its simplicity. Experimental results confirm the validity of the analytical derivations and also high robustness against common attacks. ©... 

    Implementation of a jpeg object-oriented ASIP: A case study on a system-level design methodology

    , Article 17th Great Lakes Symposium on VLSI, GLSVLSI'07, Stresa-Lago Maggiore, 11 March 2007 through 13 March 2007 ; 2007 , Pages 329-334 ; 159593605X (ISBN); 9781595936059 (ISBN) Mohammadzadeh, N ; Najafvand, M ; Hessabi, S ; Goudarzi, M ; Sharif University of Technology
    2007
    Abstract
    In this paper, we present a JPEG decoder implemented in our ODYSSEY design methodology. We start with an object-oriented JPEG decoder model. The total operation from modeling to implementation is done automatically by our EDA tool-set in about 10 hours. The resultant system is a JPEG decoder ASIP whose hardware part is implemented on FPGA logic blocks and software part runs on a MicroBlaze processor. This ASIP can be extended by software routines to implement the motion JPEG or MPEG2 decoding algorithms. We implemented our system on ML402 FPGA-based prototype board. Experimental results show that our ASIP implementation is comparable to other approaches while our approach enables quick and... 

    On the Applications of Grobner Basis

    , M.Sc. Thesis Sharif University of Technology Parviz, Maghsoud (Author) ; Pournaki, Mohammad Reza (Supervisor)
    Abstract
    Grobner bases were introduced by Bruno Buchberger in 1965. The terminology acknowledges the influence of Wolfgang Grobner on Buchberger’s work. He introduced a specific generator for ideals in the ring of polynomials over a field and then gave an algorithm for computing of that generator. It leads to solutions to a large number of algorithmic problems that are related to polynomials in several variables. Most notably, algorithms that involve Grobner basis computations allow exact conclusions on the solutions of systems of nonlinear equations, such as the (geometric) dimension of the solution set,the exact number of solutions in case there are finitely many, and their actual computation with... 

    Design and Implementation of Decoder and Encoder for Error Detecting and Correcting Algorithms for RF Links in Networks on Chip

    , M.Sc. Thesis Sharif University of Technology Sharifnia, Shahram (Author) ; Hesabi, Shaahin (Supervisor)
    Abstract
    In the upward trend of advancing technologies in chips manufacturing, utilizing Network on Chip (NOC) solutions is a sensible approach towards overcoming challenges in System on Chip (SOC). The most common form of NOC is the Wired NOC. The continuous physical size reduction of electronic circuits has led to bandwidth deficiency as well as increased temperature in various parts of these circuits. The vast advancement in chips manufacturing industry has made it possible to embed and adapt telecommunication equipment into chips, giving rise to Wireless NOC (WNOC) manufacturing. However, wireless communication increases fault rate; thereby, the system becomes more vulnerable against transient... 

    Analysis and Comparison of Different Approaches to Testing Representational Models for Brain Activity Patterns

    , M.Sc. Thesis Sharif University of Technology Mirzazadeh, Pouneh (Author) ; Sharifitabar, Mohsen (Supervisor) ; Nili, Hamed (Co-Supervisor)
    Abstract
    The representation concept links the information processed by the brain back to the world and enables us to understand what the brain does at a functional level.Representational models specify how activity patterns in the population of neurons relate to sensory stimuli, motor responses, or cognitive processes. In an experimental context, representational models can be defined as hypotheses about the distribution of activity profiles across experimental conditions. Three different methods are currently being used to test such hypotheses: encoding analysis, pattern component modeling (PCM), and representational similarity analysis (RSA). All three evaluate the second moment of the distribution... 

    Efficient secure channel coding scheme based on low-density Lattice codes

    , Article IET Communications ; Volume 10, Issue 11 , 2016 , Pages 1365-1373 ; 17518628 (ISSN) Hooshmand, R ; Aref, M. R ; Sharif University of Technology
    Institution of Engineering and Technology  2016
    Abstract
    In this study, the authors introduce an efficient secure channel coding (joint cryptography-channel coding) scheme based on Latin square low-density lattice codes (Latin square LDLCs) over unconstrained power additive white Gaussian noise channel. They benefit the properties of Latin square LDLCs to dramatically reduce the key size of the proposed scheme while having an acceptable level of security compared with previous similar schemes. To reduce the key size, they consider two approaches: (i) saving the generating sequence of parity-check matrix of used Latin square LDLC as the part of secret key set; (ii) employing the Hermite normal form of the generator matrix of used Latin square LDLC... 

    An efficient max-log MAP algorithm for VLSI implementation of turbo decoders

    , Article Proceedings - IEEE International Symposium on Circuits and Systems, 24 May 2015 through 27 May 2015 ; Volume 2015-July , 2015 , Pages 1794-1797 ; 02714310 (ISSN) ; 9781479983919 (ISBN) Ardakani, A ; Shabany, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Long term evolution (LTE)-advanced aims the peak data rates in excess of 3 Gbps for the next generation wireless communication systems. Turbo codes, the specified channel coding scheme in LTE, suffers from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple Maximum a Posteriori (MAP) cores in parallel, resulting in a large area overhead, a big drawback. The scaled Max-log MAP algorithm is a common approach to implement the MAP algorithm due to its efficient architecture with its acceptable performance. Although many works have been reported to reduce the area of the MAP unit, an efficient VLSI... 

    Distribution independent blindwatermarking

    , Article Proceedings - International Conference on Image Processing, ICIP, 7 November 2009 through 10 November 2009, Cairo ; 2009 , Pages 125-128 ; 15224880 (ISSN); 9781424456543 (ISBN) Sahraeian, M. E ; Akhaee, M. A ; Marvasti, F ; IEEE Signal Processing Society; The Institute of Electrical and Electronics Engineers ; Sharif University of Technology
    IEEE Computer Society  2009
    Abstract
    In this paper, a new blind scaling based watermarking approach is presented. The host signal is assumed to be stationary Gaussian with first-order autoregressive model. Partitioning the host signal into two separate parts, the data is embedded in one part and the other is kept unchanged for blind parameter estimation. Driving the distribution of the decision variable we have suggested a maximum likelihood decoding algorithm which is independent of the host signal distribution and can be applied for any transform domains. The proposed algorithm is applied to both artificial Gaussian autoregressive signals as well as various test images. Experimental results confirm the independence of the... 

    Heuristic guess-and-determine attacks on stream ciphers

    , Article IET Information Security ; Volume 3, Issue 2 , 2009 , Pages 66-73 ; 17518709 (ISSN) Ahmadi, H ; Eghlidos, T ; Sharif University of Technology
    2009
    Abstract
    Guess-and-determine (GD) attacks are general attacks on stream ciphers, which have often been implemented in an ad hoc manner. The authors introduce a heuristic approach to the design of GD attacks, that is a dynamic programming method using a Viterbi-like algorithm which is a well-known decoding algorithm for convolutional codes. The authors also show that with this method, the resulting GD attacks, named heuristic GD (HGD) attacks, on TIPSY, SNOW1 and SNOW2 lead to less computational complexity than the previously known GD attacks. The main advantage of HGD attacks, over ad hoc GD attacks, is that while being powerful, they can be designed algorithmically for classes of stream ciphers,... 

    A novel area-efficient VLSI architecture for recursion computation in LTE turbo decoders

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 62, Issue 6 , 2015 , Pages 568-572 ; 15497747 (ISSN) Ardakani, A ; Shabany, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are α and β recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing....