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    Design of a Non-Bianry Analog to Digital Converterfor Impantable Neural Recording Microsystem

    , M.Sc. Thesis Sharif University of Technology Eslampanah Sendi, Mohammad Sadegh (Author) ; Sharifkhani, Mohammad (Supervisor) ; Sodagar, Amir Masoud (Supervisor)
    Abstract
    A new structure of implantable neural recording microsystem base on multiple valued logic (MVL) has been proposed. MVL is a new idea for reduction of occupied area and the power consumption of microelectronic. In another side, in implantable microsystems , occupied area and power consumption by this type of micro systems is a challenging problem in this field. Therefore, the problem of power consumption and occupied area can introduce as a prime stage of suggested microsystem completed design of convertor of analog to digital in usage of multiple level in this micro system worked. Design of convertor of analog to digital is a convertor of quaternary successive approximation. And also,... 

    Circuit and Systematic Design of Low Power SAR ADC

    , M.Sc. Thesis Sharif University of Technology Yazdani, Behnam (Author) ; Sharif Khani, Mohammad (Supervisor)
    Abstract
    Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog... 

    Circuit & Systematic Design of Low Power & High Speed SAR ADC

    , M.Sc. Thesis Sharif University of Technology Khorami, Ata (Author) ; Sharifkhani, Mohammad (Supervisor)
    Abstract
    SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
    The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a... 

    Efficient Circuit and Systematic Design of Successive Approximation Register Analog to Digital Converters

    , Ph.D. Dissertation Sharif University of Technology Khorami, Ata (Author) ; Sharifkhani, Mohammad (Supervisor)
    Abstract
    Successive Approximation Register (SAR) Analog to Digital Converter (ADC) converts an analog signal to a digital code based on binary search. In contrast to other converters, such as Pipeline and Flash ADCs, most of the SAR ADC components are digital, hence, SAR ADC is technology scalable. Therefore, designed using smaller tehcnologies, SAR ADCs are able to operate at a higher frequency with a lower power consumption and area. The main focus of this thesis is to reduce power consumption, although the proposed techniques and circuits are able to improve other features such as precision, area, or speed.Considering Digital to Analog Converter (DAC), a low-power structure and a novel method to... 

    A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology

    , Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) Heydarzadeh, S ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
    Elsevier Ltd  2019
    Abstract
    A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The... 

    5-6 GHz dual-vector phase shifter in 0.18 μm LID CMOS

    , Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 82-86 ; 9781728115085 (ISBN) Choopani, A ; Fakharzadeh, M ; Safarian, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively  

    A compact mixer and DAC for implementation of a direct conversion OQPSK transmitter

    , Article 2007 IEEE Region 10 Conference, TENCON 2007, Taipei, 30 October 2007 through 2 November 2007 ; 2007 ; 1424412722 (ISBN); 9781424412723 (ISBN) Chahardori, M ; Mehrmanesh, S ; Zamanlooy, B ; Atarodi, M ; Sharif University of Technology
    2007
    Abstract
    A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power...