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    Leak-Gauge: A late-mode variability-aware leakage power estimation framework

    , Article Microprocessors and Microsystems ; Volume 37, Issue 8 PARTA , 2013 , Pages 801-810 ; 01419331 (ISSN) Assare, O ; Momtazpour, M ; Goudarzi, M ; Sharif University of Technology
    2013
    Abstract
    Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

    A comparative study of NEGF and DDMS models in the GAA silicon nanowire transistor

    , Article International Journal of Electronics ; Volume 99, Issue 9 , 2012 , Pages 1299-1307 ; 00207217 (ISSN) Hosseini, R ; Fathipour, M ; Faez, R ; Sharif University of Technology
    Abstract
    In this article, we have used quantum and semiclassical models to analyse the electrical characteristics of gate all around silicon nanowire transistor (GAA SNWT). A quantum mechanical transport approach based on non-equilibrium Green's function (NEGF) method with the use of mode space approach in the frame work of effective mass theory has been employed for this analysis. Semiclassical drift diffusion mode space (DDMS) approach has also been used for the simulation of GAA SNWT. We have studied the short-channel effects on the performance of GAA SNWT and evaluated the variation of the threshold voltage, the subthreshold slope (SS), the leakage current and the drain-induced barrier lowering... 

    Accurate estimation of leakage power variability in sub-micrometer CMOS circuits

    , Article Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012 ; 2012 , Pages 18-25 ; 9780769547985 (ISBN) Assare, O ; Momtazpour, M ; Goudarzi, M ; Sharif University of Technology
    2012
    Abstract
    Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical...