Sharif Digital Repository

A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-ampli-fication phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%  

In this paper, a new logic style is proposed to be used in the implementation of cryptographic algorithms. The aim of this approach is to counteract power analysis attacks. The proposed technique is based on the transition signaling. In dual-rail transition logic, one-bit value is transmitted by a transition on the proper signal of a couple of wires. According to this concept, converter units and logic gates are defined; it is proposed to use flip-flops to build DTL alternative parts. Although the usage of flip-flops leads to increase the required area, experimental results show that the power consumption of DTL circuits depends on unpredictable initial state of T-flip-flops. In other words,... 

Pipelined on-chip interconnects are used in on-chip networks to increase the throughput of interconnects and to achieve freedom in choosing arbitrary network topologies. Since reliability and energy consumption are prominent issues in on-chip networks, they should be carefully considered in the design of pipelined interconnects. In this paper, ws propose the use of energy recovery techniques to construct low energy and reliable pipelined on-chip interconnects. The proposed designs have been evaluated using detailed SPICE simulations. In the reliability analysis, the SEU fault model is considered as it is a major reliability concern in the sequential circuits (pipelining memory elements)... 

Technology scaling increases clock rates and die sizes; therefore, power dissipation is predicted to soon become the key limiting factor on the performance of single-chip designs. NoC as an efficient and scalable on-chip communication architecture for SoC architectures, enables integration of a large number of computational and storage blocks on a single chip. Since different applications impose different traffic models to the network, in this paper we will analyze the power and energy consumption of the most popular traffic models, i.e., Uniform, Local, HotSpot and First Matrix Transpose, in two famous and well designed topologies, mesh and torus. We will also compare these topologies with... 

In this paper, we propose a new voltage controlled oscillator (VCO) with a high oscillation frequency yet low power consumption. The oscillator which is a single stage circuit has a low phase noise due to reduced noise sources. To evaluate the performance parameters, the oscillator was simulated in a 0.18-μm standard CMOS process. The results show that the oscillation frequency of VCO may vary between 4.66-5.9 GHz. Also, the phase noise of the VCO at oscillation frequency of 5.6 GHz is -99.7 dBc at 1 MHz offset frequency. Also, the power consumption was 4.8 mW at the same oscillation frequency. © 2007 IEEE  

Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. Much research has been done in this field of study recently, e.g. in routing algorithms, switching methods, VLSI Layout, and effects of resource allocation on system performance. On the other hand, three-dimensional integrated circuits allow a time-warp for Moore's Law. By vertically stacking two or more silicon wafers, connected with a high-density, high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. In this paper, we examine performance and power consumption in a three dimensional network-on-chip structure under different types of traffic loads,... 

this paper presents a new class AB circuit for current-mode signal processing. The proposed circuit provides high-dynamic range, low distortion and accurate definition of quiescent current and it is well suited for high-speed applications. A third-order low-pass filter with a cutoff frequency of 200MHz and 51dB dynamic range is also presented. The Alter consumes 2.7mW from 1.8V supply. © 2007 IEEE  

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different... 

This paper proposes a new medium-access control (MAC) protocol designed for wireless sensor networks. A wireless sensor network is an array of large number of sensors interconnected by a multi-hop ad-hoc network. The fundamental objective for sensor network is low-power consumption while latency is usually less important. This characteristic of sensor network motivates different MAC laver design from the conventional wireless network to reduce power consumption. In this paper novel algorithm based on distributed mediation device (DMD) protocol has been introduced that utilized distributed node scheduling strategy to dramatically increase energy saving principally in intermediate devices... 

This paper presents a new method for the design of variable fractional delay (VFD) FIR digital filters using Genetic Algorithm (GA). Each sub-filter of Farrow structure is designed individually with defined accuracy and bandwidth. A variable mutation probability is also employed, which improves the accuracy of the solution. Compared with existing methods, it reduces the computational complexity and enhances the design flexibility. Furthermore, a simple GA is used to compute the filter coefficients in canonic singed digit (CSD) representations. Since this algorithm selects the initial population in CSD representation and searches for the digits between [-1 1], most of the digits become zero.... 

In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

In this brief, we present a fine-grained dark silicon architecture to facilitate further integration of transistors in static random access memory-based reconfigurable devices. In the proposed architecture, we present a technique to power off inactive configuration cells in nonutilized or underutilized logic blocks. We also propose a routing circuitry capable of turning off the configuration cells of connection blocks (CBs) and switch boxes (SBs) in the routing fabric. Experimental results carried out on the Microelectronics Center of North Carolina benchmark show that power consumption in configuration cells of lookup tables, CBs, and SBs can, on average, be reduced by 27%, 75%, and 4%,... 

In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file, to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. © 2019 Elsevier B.V  

Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh topologies, other structures can also be considered especially in 3D VLSI design. The Kautz topology is one of the interconnection architectures for multiprocessors. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the Kautz topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation. ©2008 IEEE  

This paper introduces a stochastic dynamic power management policy for soft real-time systems. Such a system comprises a single processor with the capability of dynamic voltage scaling (DVS). The policy uses DVS to consume less power in the processor while satisfying some performance constraints. The idea is based on a Markovian model of the system, which presents an analytical technique for tuning the system parameters and evaluating the effectiveness of the policy. Real-time jobs arrive according to a Poisson process and have exponentially distributed service times and relative deadlines. The power management policy is designed to reduce the long-run power consumption of the system while...