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    Low-power technique for dynamic comparators

    , Article Electronics Letters ; Volume 52, Issue 7 , 2016 , Pages 509-511 ; 00135194 (ISSN) Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Institution of Engineering and Technology 
    Abstract
    A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-ampli-fication phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%  

    Dual-rail transition logic: A logic style for counteracting power analysis attacks

    , Article Computers and Electrical Engineering ; Volume 35, Issue 2 , 2009 , Pages 359-369 ; 00457906 (ISSN) Moradi, A ; Shalmani, M. T .M ; Salmasizadeh, M ; Sharif University of Technology
    2009
    Abstract
    In this paper, a new logic style is proposed to be used in the implementation of cryptographic algorithms. The aim of this approach is to counteract power analysis attacks. The proposed technique is based on the transition signaling. In dual-rail transition logic, one-bit value is transmitted by a transition on the proper signal of a couple of wires. According to this concept, converter units and logic gates are defined; it is proposed to use flip-flops to build DTL alternative parts. Although the usage of flip-flops leads to increase the required area, experimental results show that the power consumption of DTL circuits depends on unpredictable initial state of T-flip-flops. In other words,... 

    SEU-hardened energy recovery pipelined interconnects for on-chip networks

    , Article 2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008, Newcastle upon Tyne, 7 April 2008 through 11 April 2008 ; 2008 , Pages 67-76 ; 0769530982 (ISBN); 9780769530987 (ISBN) Ejlali, A ; Al Hashimi, B. M ; Sharif University of Technology
    2008
    Abstract
    Pipelined on-chip interconnects are used in on-chip networks to increase the throughput of interconnects and to achieve freedom in choosing arbitrary network topologies. Since reliability and energy consumption are prominent issues in on-chip networks, they should be carefully considered in the design of pipelined interconnects. In this paper, ws propose the use of energy recovery techniques to construct low energy and reliable pipelined on-chip interconnects. The proposed designs have been evaluated using detailed SPICE simulations. In the reliability analysis, the SEU fault model is considered as it is a major reliability concern in the sequential circuits (pipelining memory elements)... 

    Power and performance efficient partial circuits in packet-switched networks-on-chip

    , Article Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013 ; 27 February - 1 March , 2013 , pp. 509-513 ; Print ISBN: 9781467353212 Teimouri, N ; Modarressi, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

    Power-efficient deterministic and adaptive routing in torus networks-on-chip

    , Article Microprocessors and Microsystems ; Vol. 36, issue. 7 , October , 2012 , pp. 571-585 ; ISSN: 01419331 Rahmati, D ; Sarbazi-Azad, H ; Hessabi, S ; Kiasari, A. E ; Sharif University of Technology
    Abstract
    Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

    Application specific router architectures for NoCs: An efficiency and power consumption analysis

    , Article Mechatronics ; Vol. 22, issue. 5 , August , 2012 , pp. 531-537 ; ISSN: 9574158 Najjari, N ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

    Fine-grained architecture in dark silicon era for SRAM-based reconfigurable devices

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Vol. 61, Issue. 10 , 2014 , Pages 798-802 ; ISSN: 15497747 Yazdanshenas, S ; Asadi, H ; Sharif University of Technology
    Abstract
    In this brief, we present a fine-grained dark silicon architecture to facilitate further integration of transistors in static random access memory-based reconfigurable devices. In the proposed architecture, we present a technique to power off inactive configuration cells in nonutilized or underutilized logic blocks. We also propose a routing circuitry capable of turning off the configuration cells of connection blocks (CBs) and switch boxes (SBs) in the routing fabric. Experimental results carried out on the Microelectronics Center of North Carolina benchmark show that power consumption in configuration cells of lookup tables, CBs, and SBs can, on average, be reduced by 27%, 75%, and 4%,... 

    Power and performance efficient partial circuits in packet-switched networks-on-chip

    , Article Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013 ; February , 2013 , Pages 509-513 ; 9780769549392 (ISBN) Teimouri, N ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
    2013
    Abstract
    In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

    A low power high resolution time to digital converter for ADPLL application

    , Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) Molaei, H ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    Abstract
    A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

    LTRF: enabling high-capacity register files for GPUs via hardware/software cooperative register prefetching

    , Article 23rd International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, 24 March 2018 through 28 March 2018 ; 2018 , Pages 489-502 ; 9781450349116 (ISBN) Sadrosadati, M ; Mirhosseini, A ; Ehsani, S. B ; Sarbazi Azad, H ; Drumond, M ; Falsafi, B ; Ausavarungnirun, R ; Mutlu, O ; Sharif University of Technology
    Association for Computing Machinery  2018
    Abstract
    Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file, to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

    A low-power dynamic comparator for low-offset applications

    , Article Integration ; Volume 69 , 2019 , Pages 23-30 ; 01679260 (ISSN) Khorami, A ; Saeidi, R ; Sachdev, M ; Sharifkhani, M ; Sharif University of Technology
    Elsevier B.V  2019
    Abstract
    In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. © 2019 Elsevier B.V  

    The kautz mesh: a new topology for SoCs

    , Article 2008 International SoC Design Conference, ISOCC 2008, Busan, 24 November 2008 through 25 November 2008 ; Volume 1 , 2008 , Pages I300-I303 ; 9781424425990 (ISBN) Sabbaghi Nadooshan, R ; Sarbazi Azad, H ; Sharif University of Technology
    2008
    Abstract
    Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh topologies, other structures can also be considered especially in 3D VLSI design. The Kautz topology is one of the interconnection architectures for multiprocessors. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the Kautz topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation. ©2008 IEEE  

    Stochastic DVS-based dynamic power management for soft real-time systems

    , Article Microprocessors and Microsystems ; Volume 32, Issue 3 , 2008 , Pages 121-144 ; 01419331 (ISSN) Kargahi, M ; Movaghar, A ; Sharif University of Technology
    2008
    Abstract
    This paper introduces a stochastic dynamic power management policy for soft real-time systems. Such a system comprises a single processor with the capability of dynamic voltage scaling (DVS). The policy uses DVS to consume less power in the processor while satisfying some performance constraints. The idea is based on a Markovian model of the system, which presents an analytical technique for tuning the system parameters and evaluating the effectiveness of the policy. Real-time jobs arrive according to a Poisson process and have exponentially distributed service times and relative deadlines. The power management policy is designed to reduce the long-run power consumption of the system while... 

    A high data-rate energy-efficient interference-tolerant fully integrated CMOS frequency channelized UWB transceiver for impulse radio

    , Article IEEE Journal of Solid-State Circuits ; Volume 43, Issue 4 , 2008 , Pages 974-980 ; 00189200 (ISSN) Medi, A ; Namgoong, W ; Sharif University of Technology
    2008
    Abstract
    A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25-4.75 GHz band designed for low power and high data rate communication is implemented in 0.18 μm CMOS technology. When operating at 1 Gbps data rate, it dissipates 98 mW (98 pJ/b) in the receive-mode and 108 mW (108 pJ/b) in the transmit-mode from a 1.8 V supply [1]. Compared to UWB transceivers reported in the literature, this chip dissipates the lowest energy per bit. In addition, the combination of the frequency channelized architecture, high-linearity RF circuits, aggressive baseband filtering, and low local oscillator spurs results in an interference-tolerant receiver that is able to co-exist with systems operating... 

    The 2D digraph-based NoCs: Attractive alternatives to the 2D mesh NoCs

    , Article Journal of Supercomputing ; Vol. 59, issue. 1 , January , 2012 , pp. 1-21 ; ISSN: 9208542 Sabbaghi-Nadooshan, R ; Modarressi, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    This paper proposes two-dimensional directed graphs (or digraphs for short) as a promising alternative to the popular 2D mesh topology for networks-onchip (NoCs). Mesh is the most popular topology for the NoCs, mainly due to its suitability for on-chip implementation and low cost. However, the fact that a digraph offers a lower diameter than its equivalent linear array of equal cost motivated us to evaluate digraphs as the underlying topology of NoCs. This paper introduces a family of NoC topologies based on three well-known digraphs, namely de Bruijn, shuffleexchange, and Kautz. We study topological properties of the proposed topologies. We show that the proposed digraph-based topologies... 

    High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

    , Article Proceedings of the International Symposium on Low Power Electronics and Design ; 2011 , p. 79-84 ; ISSN: 15334678 ; ISBN: 9781612846590 Jadidi, A ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

    Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Vol. 29, issue. 10 , 2010 , p. 1558-1571 ; ISSN: 02780070 Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

    A comparative study of energy/power consumption in parallel decimal multipliers

    , Article Microelectronics Journal ; Vol. 45, Issue 6 , June , 2014 , pp. 775-780 Malekpour, A ; Ejlali, A ; Gorgin, S ; Sharif University of Technology
    Abstract
    Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require working with decimal numbers while it has been shown that if we convert decimal number to binary ones, this will negatively influence the preciseness required for these applications. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today's digital systems. While the energy consumption of parallel decimal multipliers has not been addressed in previous works, in this paper we present a comparative study of... 

    Power-efficient deterministic and adaptive routing in torus networks-on-chip

    , Article Microprocessors and Microsystems ; Volume 36, Issue 7 , 2012 , Pages 571-585 ; 01419331 (ISSN) Rahmati, D ; Sarbazi Azad, H ; Hessabi, S ; Kiasari, A. E ; Sharif University of Technology
    Elsevier  2012
    Abstract
    Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

    Application specific router architectures for NoCs: An efficiency and power consumption analysis

    , Article Mechatronics ; Volume 22, Issue 5 , 2012 , Pages 531-537 ; 09574158 (ISSN) Najjari, N ; Sarbazi Azad, H ; Sharif University of Technology
    Elsevier  2012
    Abstract
    Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs...