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embedded-system
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A Comparative study of joint power and reliability management techniques in multicore embedded systems
, Article 3rd CSI/CPSSI International Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2020, 10 June 2020 through 11 June 2020 ; 2020 ; Sahraee, A ; Saber Latibari, J ; Ansari, M ; Rohbani, N ; Ejlali, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2020
Abstract
Low power consumption and high-reliability are often major objectives in the design of embedded systems. To reduce power consumption, embedded systems usually employ system-level power management techniques, e.g. Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM). To achieve high reliability, embedded systems often exploit fault-tolerant techniques. Fault-tolerant techniques are in a trade-off with energy consumption, peak-power consumption, and temperature. Thus, different methods have been introduced that simultaneously consider reliability and power consumption as the system constraints. Several novel methods have been proposed in previous works to reduce the power...
In-scratchpad memory replication: Protecting scratchpad memories in multicore embedded systems against soft errors
, Article ACM Transactions on Design Automation of Electronic Systems ; Volume 20, Issue 4 , 2015 ; 10844309 (ISSN) ; Farbeh, H ; Miremadi, S. G ; Sharif University of Technology
Association for Computing Machinery
2015
Abstract
Scratchpad memories (SPMs) are widely employed inmulticore embedded processors. Reliability is one of the major constraints in the embedded processor design, which is threatened with the increasing susceptibility of memory cells to multiple-bit upsets (MBUs) due to continuous technology down-scaling. This article proposes a low-cost and efficient data replication mechanism, called In-Scratchpad Memory Replication (ISMR), to correct MBUs in SPMs of multicore embedded processors. The main feature of ISMR is a smart controller, called Replication Management Unit (RMU), which is responsible for dynamically analyzing the activity of the SPM blocks at runtime and efficiently replicating the...
High performance and predictable memory controller for multicore mixed-criticality real-time systems
, Article IET Computers and Digital Techniques ; Volume 13, Issue 5 , 2019 ; 17518601 (ISSN) ; Farbeh, H ; Sharif University of Technology
Institution of Engineering and Technology
2019
Abstract
Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In...
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
With new technologies, processor power density is dramatically increased which results in high temperature. Temperature has significant impact on reliability, performance, power consumption and cooling costs. This alarming trend underscores the importance of temperature management methods in system design. Recently, various research efforts have been focused on addressing thermal issues. Due to mobility, cost and size constraints and reliability requirements, the embedded systems do not warrant use of modern cooling mechanisms such as heat sink and fan. This caused the thermal issues to be more prominent in embedded domain. This study aims at introducing thermal management techniques for...
Reducing the Energy Overhead of Replication Mechanisms in Distributed Embedded Systems
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
Distributed embedded systems are widely used in safety-critical applications, such as avionics platform and flight control system. Faults in such applications may cause catastrophic effect. Therefore, these systems must be fault-tolerant and must be designed not only to detect faults but also to recover from faults. Fault tolerance is normally realized on multi-processor system via temporal duplication (time-redundancy) or spatial duplication (hardware-redundancy) depending on the availability of the slack time. Slack time is defined as the difference between the deadline and execution time. Duplication is a common technique to achieve fault tolerance in safety-critical applications, but may...
An FSM-based monitoring technique to differentiate between follow-up and original errors in safety-critical distributed embedded systems
, Article Microelectronics Journal ; Volume 42, Issue 6 , June , 2011 , Pages 863-873 ; 00262692 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2011
Abstract
Nowadays, distributed embedded systems are employed in many safety-critical applications such as X-by-Wire. These systems are composed of several nodes interconnected by a network. Studies show that a transient fault in the communication controller of a network node can lead to errors in the fault site node (called original errors) and/or in the neighbor nodes (called follow-up errors). The communication controller of a network node can be halted due to an error, which may be a follow-up error. In this situation, a follow-up error leads to halt the correct operation of a fault-free controller while the fault site node, i.e. the faulty controller, still continues its operation. In this paper,...
Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs
, Article Microelectronics Reliability ; Volume 47, Issue 2-3 , 2007 , Pages 461-470 ; 00262714 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2007
Abstract
Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of...
A reconfigurable cache architecture for object-oriented embedded systems
, Article 2006 Canadian Conference on Electrical and Computer Engineering, CCECE'06, Ottawa, ON, 7 May 2006 through 10 May 2006 ; 2006 , Pages 959-962 ; 08407789 (ISSN); 1424400384 (ISBN); 9781424400386 (ISBN) ; Hessabi, S ; Goudarzi, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2006
Abstract
A reconfigurable cache architecture for object-oriented application-specific instruction set processors (ASIP) is presented in this paper. The embedded ASIPs we follow in this research are specifically designed to suit object-oriented applications and are synthesized form an object-oriented highlevel specification. The ASIPs are composed of a processor core along with a number of hardware functional units. In order to support concurrent execution of the functional units, we propose a cache architecture which is virtually divided into a number of partitions. The partition sizes can be dynamically changed depending on the run-time behavior of the application. Partitioning the cache not only...
Energy-optimized on-chip networks using reconfigurable shortcut paths
, Article Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 24 February 2011 through 25 February 2011 ; Volume 6566 LNCS , February , 2011 , Pages 231-242 ; 03029743 (ISSN) ; 9783642191367 (ISBN) ; Modarressi, M ; Tavakkol, A ; Sarbazi Azad, H ; Sharif University of Technology
2011
Abstract
Topology is an important network attribute that greatly affects the power, performance, cost, and design time/effort of NoCs. In this paper, we propose a novel NoC architecture that can exploit the benefits of both application-specific and regular NoC topologies. To this end, a subset of NoC links bypass the router pipeline stages and directly connect remotely located nodes. This results in an NoC which holds both fixed connections between adjacent nodes and long connections virtually connecting non-adjacent nodes. These shortcut paths are constructed at run-time by employing a simple and fast mechanism composed of two processes: on-chip traffic monitoring and path reconfiguration. The...
A new scheme on recovery from failure in NICE overlay protocol
, Article 1st International Conference on Scalable Information Systems, InfoScale '06, Hong Kong, 30 May 2006 through 1 June 2006 ; Volume 152 , 2006 ; 1595934286 (ISBN); 9781595934284 (ISBN) ; Barghi, S ; Rabiee, H. R ; Ghanbari, M ; Sharif University of Technology
2006
Abstract
Overlay networks have been an active area of research for the past few years. The control overhead and the recovery from failure are the two important issues in the topology aware embedded overlay networks. In this research, we have introduced an enhanced version of the NICE protocol, called resilient NICE (R-NICE) that reduces the control overhead significantly. Furthermore, by saving the join path for an end host, the time and overhead of rejoining for isolated nodes have also been reduced. This will cause the clusters and consequently the overall network to become more stable and the effect of a node failure become localized. Our experimental results have confirmed the superior...
Object-aware cache: Higher hit-ratio in object-oriented ASIPs
, Article Canadian Conference on Electrical and Computer Engineering; Technology Driving Innovation, 2004, Niagara Falls, 2 May 2004 through 5 May 2004 ; Volume 2 , 2004 , Pages 0653-0656 ; 08407789 (ISSN) ; Hessabi, S ; Mycroft, A ; Sharif University of Technology
2004
Abstract
At any point in time in an object-oriented (OO) program, a class method is running whose set of unconditionally-accessed data fields can be statically determined. We propose to fetch this set prior to or during the method execution to increase the data cache hit-ratio. This requires that either the software directs the processor cache controller, or the processor is aware of the currently running class method. We follow the latter approach by extending our previous work where we introduced the object-oriented application-specific instruction processor (OO-ASIP) as a processor whose instruction-set consist of methods of a class library. Such an OO-ASIP is aware of the currently running method...
ReMap: Reliability management of peak-power-aware real-time embedded systems through task replication
, Article IEEE Transactions on Emerging Topics in Computing ; Volume 10, Issue 1 , 2022 , Pages 312-323 ; 21686750 (ISSN) ; Ansari, M ; Ejlali, A ; Sharif University of Technology
IEEE Computer Society
2022
Abstract
Increasing power densities in future technology nodes is a crucial issue in multicore platforms. As the number of cores increases in them, power budget constraints may prevent powering all cores simultaneously at full performance level. Therefore, chip manufacturers introduce a power budget constraint as Thermal Design Power (TDP) for chips. Meanwhile, multicore platforms are suitable for the implementation of fault-tolerance techniques to achieve high reliability. Task Replication is a well-known technique to tolerate transient faults. However, careless task replication may lead to significant peak power consumption. In this article, we consider the problem of achieving a given reliability...
Offline replication and online energy management for hard real-time multicore systems
, Article CSI Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2015, 7 October 2015 through 8 October 2015 ; October , 2015 , Page(s): 1 - 7 ; 9781467380478 (ISBN) ; Safari, S ; Ansari, M ; Salehi, M ; Ejlali, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
For real-time embedded systems, energy consumption and reliability are two major design concerns. We consider the problem of minimizing the energy consumption of a set of periodic real-time applications when running on a multi-core system while satisfying given reliability targets. Multi-core platforms provide a good capability for task replication in order to achieve given reliability targets. However, careless task replication may lead to significant energy overhead. Therefore, to provide a given reliability level with a reduced energy overhead, the level of replication and also the voltage and frequency assigned to each task should be determined cautiously. The goal of this paper is to...
A compile-time optimization method for WCET reduction in real-time embedded systems through block formation
, Article ACM Transactions on Architecture and Code Optimization ; Volume 12, Issue 4 , January , 2015 ; 15443566 (ISSN) ; Taram, M ; Assadi, S ; Ejlali, A ; Sharif University of Technology
Association for Computing Machinery
2015
Abstract
Compile-time optimizations play an important role in the efficient design of real-time embedded systems. Usually, compile-time optimizations are designed to reduce average-case execution time (ACET). While ACET is a main concern in high-performance computing systems, in real-time embedded systems, concerns are different and worst-case execution time (WCET) is much more important than ACET. Therefore, WCET reduction is more desirable than ACET reduction in many real-time embedded systems. In this article, we propose a compile-time optimization method aimed at reducing WCET in real-time embedded systems. In the proposed method, based on the predicated execution capability of embedded...
A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design
, Article Proceedings of the International Conference on Dependable Systems and Networks, 28 June 2010 through 1 July 2010 ; June , 2010 , Pages 131-140 ; 9781424475018 (ISBN) ; Miremadi, S. G ; Asadi, H ; Nematollah Ahmadian, S ; Sharif University of Technology
2010
Abstract
In this paper, we propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates,flip-flops, and paths of a circuit. Using such information, designers can selectively protect the vulnerable parts resulting in lower power and area overheads that are the most important factors in embedded systems. Unlike previous approaches, the proposed approach firstly does not rely on fault injection or fault simulation; secondly it measures the SER for multi cycles of circuit operation; thirdly, the proposed approach accurately computes all three masking factors, namely, logical, electrical, and timing masking; fourthly, the effects of error...
A low-cost on-line monitoring mechanism for the flexray communication protocol
, Article Proceedings - 2009 4th Latin-American Symposium on Dependable Computing, LADC 2009, 1 September 2009 through 4 September 2009, Joao Pessoa ; 2009 , Pages 111-118 ; 9780769537603 (ISBN) ; Miremadi, G ; Sharif University of Technology
2009
Abstract
Nowadays, communication protocols are used in safety-critical automotive applications. In these applications, fault tolerance is a main requirement and the existence of single points of failure is a serious threat to system failures. Among the communication protocols, FlexRay is expected to become the communication backbone for future automotive systems. In this paper, we identify single points of failure in the FlexRay protocol by injecting a total of 135,600 single-bit transient faults into all accessible registers of the FlexRay communication controller. The results showed that about 1.2% of all injected faults caused the controller to freeze immediately. Based on these results and...
Investigation and reduction of fault sensitivity in the FlexRay communication controller registers
, Article 27th International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2008, Newcastle upon Tyne, 22 September 2008 through 25 September 2008 ; Volume 5219 LNCS , 2008 , Pages 153-166 ; 03029743 (ISSN); 3540876979 (ISBN); 9783540876977 (ISBN) ; Miremadi, S. G ; Sharif University of Technology
2008
Abstract
It is now widely believed that FlexRay communication protocol will become the de-facto standard for distributed safety-critical automotive systems. In this paper, the fault sensitivity of the FlexRay communication controller registers are investigated using transient single bit-flip fault injection. To do this, a FlexRay bus network, composed of four nodes, was modeled. A total of 135,600 transient single bit-flip faults were injected to all 408 accessible single-bit and multiple-bit registers of the communication controller in one node. The results showed that among all 408 accessible registers, 30 registers were immediately affected by the injected faults. The results also showed that...
High-Performance predictable NVM-Based instruction memory for real-time embedded systems
, Article IEEE Transactions on Emerging Topics in Computing ; Volume 9, Issue 1 , 2021 , Pages 441-455 ; 21686750 (ISSN) ; Hoseinghorban, A ; Poursafaei, F ; Ejlali, A ; Sharif University of Technology
IEEE Computer Society
2021
Abstract
Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems and memory subsystem has a major impact on both of them. Therefore, many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories instead of conventional memories such as SRAM and DRAM. Indeed, the low leakage power dissipation and improved density of emerging non-volatile memories make them prime candidates for replacing the conventional memories. However, accessing these memories imposes performance and energy overhead and using them as the instruction memory could increase the worst case execution time,...
Improving Fault Tolerance in Safety-Critical Distributed Automotive Communication Networks
, Ph.D. Dissertation Sharif University of Technology ; Miremadi, Ghassem (Supervisor)
Abstract
Nowadays, distributed embedded systems are extensively employed in safety-critical automotive applications, e.g. Steer-By-Wire and Brake-By-Wire. Moreover, according to the present and future needs of the automotive industry of Iran, in this Ph.D. thesis, fault tolerance in safety-critical distributed automotive communication networks has been improved. This thesis consists of three research layers. In the first layer, several comprehensive studies on all automotive communication protocols and their architectures have been done. Among the protocols, the FlexRay communication protocol has been selected to employ in safety-critical distributed embedded systems. In the second layer, the fault...
Real-Time Scheduling in Distributed Fault-Tolerant and Low Energy Embedded Systems
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
Scheduling of real-time processes is often one of the greatest challenges in designing distributed embedded systems. Low energy consumption and fault tolerance are key objectives in the design of embedded systems. However, these objectives are at odds, and there is a trade-off between them. A large part of this thesis includes a comprehensive study on previous researches on energy consumption and fault tolerance in hard real-time embedded systems. Real-time systems usually use system level energy management methods, i.e., dynamic voltage scaling (DVS) and dynamic power management (DPM). Also hard real-time systems often use replication to achieve fault tolerance. In this thesis, we...