Sharif Digital Repository

Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand.... 

Increasing in size and complexity of digital designs has made manufacturing process more complex and enforces more complexity in verification of designs. This makes it essential to address critical verification issues at the early stages of design cycle. Such a complicated designs needs to be tested for fabrication faults as well as functional faults. Several attempts have been made to raise the quality of testing methods with automatic test pattern generation (ATPG) and design for testability (DFT) methods in logic and lower levels. Although these techniques try to increase the testability of a circuit considerably, but there are always some overheads in area, power and performance....