Search for: field-programmable-gate-array--fpga
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    Design and Simulation of Dust Control System in the Air with the FPGA

    , M.Sc. Thesis Sharif University of Technology Ghafouri, Rasool (Author) ; Vosoughi Vahdat, Bijan (Supervisor) ; Hashemi, Matin (Co-Advisor)

    Six-leg AC-AC fault tolerant converter with reduced extra-sensor number

    , Article International Review of Electrical Engineering ; Volume 6, Issue 1 , 2011 , Pages 132-138 ; 18276660 (ISSN) Shahbazi, M ; Poure, P ; Zolghadri, M. R ; Saadate, S ; Sharif University of Technology
    In order to prevent further damage and to provide the continuity of service of six-leg converter in case of open-switch fault, it is mandatory to perform fast fault detection and converter reconfiguration schemes. Extra sensors are needed to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A six-leg fault tolerant converter topology without redundancy and with bidirectional power flow is studied. First simulations are carried out to evaluate the proposed fault detection principle and the fault tolerant converter topology. The fully digital control and the fault detection are... 

    Hardware Implementation of Li-Fi System

    , M.Sc. Thesis Sharif University of Technology Sadeghi, Maryam (Author) ; Shabani, Mahdi (Supervisor) ; Kavehvash, Zahra (Co-Supervisor)
    Today, the “wireless” is used almost synonymously with radio-frequency (RF) technologies as a result of the wide-scale deployment and utilization of wireless RF devices and systems. The RF band ranges from 300 kHz to 300 GHz and its use is regulated by regional and international agencies. With the ever-growing popularity of data-heavy wireless communications, wireless products and services, the demand for RF spectrum is outstripping supply, which causes the spectrum congestion. Therefore, the time has come to seriously consider other viable options for wireless communication using the upper parts of the electromagnetic spectrum. In this way, the optical band which includes infrared, visible,... 

    Design of FPGA Cluster Platform For Cryptanalysis Applications

    , M.Sc. Thesis Sharif University of Technology Hosseini, Hamid Reza (Author) ; Jahangir, Amir Hossein (Supervisor)
    Daily improvements in technology and exchanging important information via internet and connection networks make data and connection security a significant problem. Cryptology is the branch of knowledge which concerns secret communications in all of its aspects. Two major areas of cryptology are cryptography and cryptanalysis. Cryptography is a branch of cryptology concerned with protecting communications from being read by unauthorized people.
    Cryptologists design and create algorithms to improve cryptography along with finding methods to crack those algorithms. Cryptanalysis is a branch of cryptology concerned with cracking the cryptographic systems used by others.

    Accelerated FPGA-Based NOC Simulation With Software Configuration

    , M.Sc. Thesis Sharif University of Technology Mardani Kamali, Hadi (Author) ; Hesabi, Shahin (Supervisor)
    ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
    To address these challenges, we propose a new... 

    CAD-directed SEU susceptibility reduction in FPGA circuits designs

    , Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 3675-3678 ; 02714310 (ISSN) Zarand, H. R ; Miremadi, S. G ; Pradhan, D. K ; Mathew, J ; Sharif University of Technology
    This paper presents a SEU-mitigative placement and route of circuits in the FPGAs which is based on the popular placement and route tool The tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation and no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. We have investigated the effect of this tool on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 22%. However, it increases critical path delay and... 

    Fast SEU detection and correction in LUT configuration bits of sram-based FPGAs

    , Article 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 March 2007 through 30 March 2007 ; 2007 ; 1424409101 (ISBN); 9781424409105 (ISBN) Zarandi, H.R ; Miremadi, S. G ; Argyrides, C ; Pradhan, D. K ; Sharif University of Technology
    FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any... 

    CLB-based detection and correction of bit-flip faults in SRAM-based FPGAs

    , Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 3696-3699 ; 02714310 (ISSN) Zarandi, H. R ; Miremadi, S. G ; Argyrides, C ; Pradhan, D. K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2007
    This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high energy particles, alpha and neutrons in the atmosphere. For each of protections, the applicability, efficiency and implementation issues are discussed. Moreover, the area, the power and the protection capability of the methods are mentioned and compared with previous work Based on the results of experiments and their analysis, one method is selected as best one. The selected method is much better than previous work e.g., duplication with comparison, triple modular redundancy which impose two and three area and power overheads, respectively. © 2007 IEEE  

    Implementation of the Digital Part of DVB-T Protocol with Reduced Power and Area

    , M.Sc. Thesis Sharif University of Technology Mozafari, Hassan (Author) ; Hessabi, Shaahin (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
    An implementation of Digital Section of a DVB-T receiver has been introduced in this research. Nowadays, low-power and area-efficient designs have proven their importance in IC design aspect, so many low-power and area efficient approaches have been considered in this implementation. This design has been segregated into independent blocks, and each of them has been designed respect to the design goals. After that, all these blocks linked together and a whole system design implemented in gate level, then downloaded into a FPGA (Field programmable Gate Array) to test the timing and functionality of implemented blocks. In this thesis, some innovations have been introduced. A new algorithm for... 

    Design and Implementation of 2.5 Gbps Circuit Switching Fabric

    , M.Sc. Thesis Sharif University of Technology Jahani, Sohrab (Author) ; Pakravan, Mohammad Reza (Supervisor) ; Movahhedy, Mohammad Reza (Supervisor)
    Providing high bandwidth network infrastructures for ever increasing need of data transport is of great importance. The underling infrastructure for many communication services such as GSM/3G/4G mobile networks and Internet services is Synchronous Digital Hierarchy (SDH) optical transport systems. SDH are standardized protocols that multiplex multiple lower rate digital bit streams, such as E1 and Ethernet, and transfer them synchronously over optical fiber using lasers or LEDs. In addition to high data transfer rates, flexible network management and protection mechanisms have great importance, hence are part of SDH standards. In order to obtain flexible network architecture and protected... 

    System Level Modeling and Optimization of Accelerator-CPU Communication in Data Centers

    , M.Sc. Thesis Sharif University of Technology Haji Ali Khamseh, Amir (Author) ; Goudarzi, Maziar (Supervisor)
    Due to the data centers rapid growth and introduction of a new basic type of massive data processing platforms which requires accelerators to speedup computation and enhance the efficiency and reduce power consumption, using accelerators is inevitable. Communication and data transfer time between software and hardware is the most of time spent on the use of accelerators. By optimizing this part of the hardware / software platform, we have achieved substantial results in this area. The aim of our study is to organize a survey of real accelerator characteristics. To figure out its defects and main drawbacks, in addition to improving the overall efficiency of system. The implementation of... 

    Designing a 32-Bit Fault-Tolerant ALU Using EDAC

    , M.Sc. Thesis Sharif University of Technology (Author) ; Vosughi Vahdat, Bijan (Supervisor) ; Mortazavi, Mohammad (Supervisor)

    Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since... 

    An Efficient Reconfigurable Architecture in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Tamimi, Sajjad (Author) ; Asadi, Hossein (Supervisor)
    Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, Field-Programmable Gate Arrays (FPGAs) are used in industry for implementing either an entire embedded system or a Hardware Description Language (HDL)-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors. In this thesis, we present an efficient reconfigurable architecture to implement embedded processors in... 

    Accelerating Network Firewalls

    , M.Sc. Thesis Sharif University of Technology Milanian, Zhaleh (Author) ; Goudarzi, Maziar (Supervisor)
    With the proliferation of Internet-based applications and malicious attacks, security has become one of the most influential aspects in the network and, it should be considered from the beginning steps of designing the network infrastructure. Based on the fact that pattern matching is considered as one of the most important roles of security devices or applications, it becomes an important procedure in firewalls that have been classified as security equipments which adopt a security mechanism in order to restrict the traffic exchanged between networks and particular users or certain applications. While the trend of using compressed traffic is drastically increasing, this type of traffic is... 

    FPGA-based Fault Injection for Evaluating the Fault Tolerance of Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Mohammadi, Abbas (Author) ; Ejlali, Alireza (Supervisor)
    One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a... 

    Design of Fault-tolerance Mechanisms for Soft Multiprocessors

    , M.Sc. Thesis Sharif University of Technology Zabihi, Masoumeh (Author) ; Miremadi, Ghasem (Supervisor)
    Increasing complexity of embedded systems and the need for more computation powerhave directed designers toward using of multiprocessors. SRAM-based FPGAs are suitable platforms for implementation of multiprocessors due to thier low cost, fast time-to-market and re-configurability. FPGA-based multiprocessors are known as soft multiprocessors. The large area of SRAM-based FPGAs is occupied by configuration bits. Configuration bits are vulnerable to high energy particles that can lead to soft errors. In this regards, it is of decisive importance to protect soft multiprocessors against soft errors. This thesis proposes a fault-tolerant method for soft multiprocessors that can detect and... 

    Design of Telecommand Subsystem of a LEO Satellite Based on the FPGA

    , M.Sc. Thesis Sharif University of Technology Bolandi, Ali (Author) ; Vosoghi, Bijan (Supervisor)
    Achieving technical knowledge and technology of design, build, test and launch satellites in each country is a strategic issue due to extension of satellite applications in various aspects of human life. One of the most important subsystems of a satellite is the telecommand part. This part is responsible for decode, receive, interpret, and distribution of commands and data received from the ground station. This part in terms of reliability is the most critical part of satellite because it coordinates satellite and ground station and also is the part which should be turned on during the mission and controls other parts of satellite. In other words this part should be design with high... 

    Implementing a Software-Defined-Network Firewall on FPGA

    , M.Sc. Thesis Sharif University of Technology Daneshmand, Arash (Author) ; Jahangir, Amir Hossein (Supervisor)
    Software defined networks are developed to provide programmability and a centralized view in networks by decoupling control plane from data plane. Software defined networks are now well received,and these networks are evolving every day. This is while more attention has been paid to widen the application of these networks and eliminating the shortcomings in their performance. On the other hand, in very large networks, the issue of efficiency and processing speed is of great importance. However, performance in these networks is not satisfactory, especially in single controller based SDN due to the complex processing of packets in a unique controller. Security needs are also of great... 

    Analyzing area penalty of 32-bit fault tolerant ALU using BCH code

    , Article Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, 31 August 2011 through 2 September 2011, Oulu ; 2011 , Pages 409-413 ; 9780769544946 (ISBN) Khorasani, V ; Vahdat, B. V ; Mortazavi, M ; Sharif University of Technology
    In this paper we have presented a hardware implementation of 32-bit Fault-tolerant ALU (Arithmetic and Logic Unit) which is compared with the current techniques, Residue code, Triple Modular Redundancy (TMR) with single voting and TMR with triplicated voter that are widely used in space application to mitigate the upsets, in terms of area penalty. We consider BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA (Field Programmable Gate Array). The new implementation of ALU employing BCH code on Spartan-3 FPGA has been provided. The results show that our fault tolerant method has the lowest hardware overhead and it can correct any 5-bit error in any... 

    Dynamic FPGA-accelerator sharing among concurrently running virtual machines

    , Article Proceedings of 2016 IEEE East-West Design and Test Symposium, EWDTS 2016, 14 October 2016 through 17 October 2016 ; 2017 ; 9781509006939 (ISBN) Nasiri, H ; Goudarzi, M ; Sharif University of Technology
    Using an FPGA as a hardware accelerator has been prevalent, to speed up compute intensive workloads. However, employing an accelerator in virtualized environment enhances complexity, because accessing the accelerator from virtual machines has significant overhead and sharing it needs some considerations. We have implemented adequate infrastructure to share an FPGA-based accelerator between multiple virtual machines with negligible access overhead which dynamically implements virtual machines' accelerators. In our architecture each user process from a virtual machine can directly access the FPGA over PCIe link and reconfigure its accelerator in the specified part of FPGA at run-time. The...