Search for: hardware
0.017 seconds
Total 350 records

    Trojan counteraction in hardware: A survey and new taxonomy

    , Article Indian Journal of Science and Technology ; Volume 9, Issue 18 , 2016 ; 09746846 (ISSN) Bazzazi, A ; Manzuri Shalmani, M. T ; Hemmatyar, A. M. A ; Sharif University of Technology
    Indian Society for Education and Environment  2016
    The widespread expansion of the semiconductor industry and various production phases have led to the increased importance of fabricating highly secure chips. Both in factories manufacturing and later at actual operation, digital integrated circuits (IC) might encounter a variety of hardware attacks, one type of which involves Hardware Trojans (HT). Due to their diversity, it has become a major hardware security challenge to prevent, detect and track down HTs. In this regard, the first step is to understand the taxonomy of Trojans and the current ways in which they can be encountered. For that purpose, certain classifications are required. With their downsized dimensions, the Trojans have... 

    Behavioral-level hardware trust: analysis and enhancement

    , Article Microprocessors and Microsystems ; Volume 58 , 2018 , Pages 24-33 ; 01419331 (ISSN) Farajipour Ghohroud, N ; Hessabi, S ; Sharif University of Technology
    Elsevier B.V  2018
    Hardware IPs are mostly presented in Register Transfer Level (RTL) description. Although considerable attention has been paid to hardware Trojan detection and design-for-trust at gate level and lower levels, so far there have been few methods at RT Level and behavioral RTL. We propose an approach to analyze circuit susceptibility to Trojan at the behavioral level, based on controllability analysis. We propose three design-for-trust methods, which reduce circuit vulnerability to hardware Trojans by increasing the probability of Trojan detection. We use side-channel Trojan detection method based on power consumption to evaluate Trojan detection probability. Our proposed methods can improve... 

    Mixed analog-digital crossbar-based hardware implementation of sign-sign LMS adaptive filter

    , Article Analog Integrated Circuits and Signal Processing ; 2010 , Pages 1-8 ; 09251030 (ISSN) Merrikh Bayat, F ; Bagheri Shouraki, S ; Sharif University of Technology
    Recently announcement of a physical realization of a fundamental circuit element called memristor by researchers at Hewlett Packard (HP) has attracted so much interest worldwide. Combination of this newly found element with crossbar interconnect technology, opened a new field in designing configurable or programmable electronic systems which can have applications in signal processing and artificial intelligence. In this paper, based on the simple memristor crossbar structure, we will propose a new mixed analog-digital circuit as a hardware implementation of the sign-sign least mean square (LMS) adaptive filter algorithm. In this proposed hardware, any multiplication and addition is performed... 

    A novel hardware implementation of ids method

    , Article IEICE Electronics Express ; Volume 6, Issue 23 , 2009 , Pages 1626-1630 ; 13492543 (ISSN) Tarkhan, M ; Bagheri Shouraki, S ; Khasteh, S. H ; Sharif University of Technology
    ALM is an adaptive recursive algorithm which tries to express a multi-input multi-output system as a fuzzy combination of some single-input single-output systems. It uses a fuzzy curve fitting technique for behavior extraction or finding the input-output transfor-mation of each of the single-input single-output systems, which called ink drop spread (IDS). In this paper we present a new implementation of a hardware unit implementing the ink drop spread (IDS) method  

    Hardware trojan detection based on logical testing

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 33, Issue 4 , 2017 , Pages 381-395 ; 09238174 (ISSN) Bazzazi, A ; Manzuri Shalmani, M. T ; Hemmatyar, A. M. A ; Sharif University of Technology
    Springer New York LLC  2017
    In recent years, hardware Trojans (HTs) have become one of the main challenging concerns within the chain of manufacturing digital integrated circuit chips. Because of their diversity in chips, HTs are difficult to detect and locate. This paper attempted to propose a new improved method for detection and localization of HTs based on the real-time logical values of nodes. The algorithm extracts the nodes with special attributes. At the next stage, the nodes with the greatest similarity in terms of logical value are selected as targets. Depending on the size of the circuit, the extraction continues until a sufficient number of similar nodes has been selected. The logical relationship between... 

    A new architecture for analog sampled-data neural filters

    , Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 2494-2497 ; 02714310 (ISSN) Sedighi, B ; Analui, B ; Sharif Bakhtiar, M ; Sharif University of Technology
    A new architecture for analog sampled-data filters is presented. This architecture is based on implementing the difference equation of the filter using a neural network. It results in lower sensitivity of filter coefficients to hardware nonidealities. Different tradeoffs in the hardware implementation of the filter are discussed. A design example is also presented. © 2005 IEEE  

    Reliable hardware architectures for efficient secure hash functions ECHO and fugue

    , Article 15th ACM International Conference on Computing Frontiers, CF 2018, 8 May 2018 through 10 May 2018 ; 2018 , Pages 204-207 ; 9781450357616 (ISBN) Mozaffari Kermani, M ; Azarderakhsh, R ; Bayat Sarmadi, S ; ACM Special Interest Group on Microarchitectural Research and Processing (SIGMICRO) ; Sharif University of Technology
    Association for Computing Machinery, Inc  2018
    In cryptographic engineering, extensive attention has been devoted to ameliorating the performance and security of the algorithms within. Nonetheless, in the state-of-the-art, the approaches for increasing the reliability of the efficient hash functions ECHO and Fugue have not been presented to date.We propose efficient fault detection schemes by presenting closed formulations for the predicted signatures of different transformations in these algorithms. These signatures are derived to achieve low overhead for the specific transformations and can be tailored to include byte/word-wide predicted signatures. Through simulations, we show that the proposed fault detection schemes are... 

    A bio-inspired method for hardware Trojan detection

    , Article 2017 19th International Symposium on Computer Architecture and Digital Systems, CADS 2017 ; Volume 2018-January , 8 March , 2018 , Pages 1-2 ; 9781538643792 (ISBN) Farajipour Ghohroud, N ; Hessabi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Outsourcing the ICs for manufacturing introduces potential security threats such as hardware Trojans (HTs). In this paper, we propose hardware-based artificial immune system for solving this problem. This system uses a biologically-inspired technique which makes it attractive for using in computer security systems. Using our proposed method, the probability of HT detection can reach 100 percent, and the system can be made immune against HTs. © 2017 IEEE  

    Trustworthiness Improvement of Integrated Circuits against Hardware Trojans

    , Ph.D. Dissertation Sharif University of Technology Farajipour Ghohroud, Najmeh (Author) ; Hessabi, Shaahin (Supervisor)
    Most hardware manufacturers outsource the fabrication of their integrated circuits (ICs) to third party foundries in order to reduce the cost of silicon chip fabrication. This increases the vulnerability to malicious activities. Third party foundries may modify the circuit’s design or its physical parameters. These modifications are known as Hardware Trojan Horses (HTHs). An adversary can insert a Trojan in the design to disable and/or destroy a system, or leak information to the adversary. Several Methods are proposed for HTH Detection, and Design for Hardware Trust (DfHT) in the last decade. However, the lack of a comprehensive approach in this area is sensed. Moreover, the previously... 

    Memristive fuzzy edge detector

    , Article Journal of Real-Time Image Processing ; Vol. 9, issue. 3 , September , 2014 , pp. 479-489 ; Online ISSN: 1861-8219 Merrikh-Bayat, F ; Bagheri Shouraki, S ; Merrikh-Bayat, F ; Sharif University of Technology
    Fuzzy inference systems always suffer from the lack of efficient structures or platforms for their hardware implementation. In this paper, we tried to overcome this difficulty by proposing a new method for the implementation of the fuzzy rule-based inference systems. To achieve this goal, we have designed a multi-layer neuro-fuzzy computing system based on the memristor crossbar structure by introducing a new concept called the fuzzy minterm. Although many applications can be realized through the use of our proposed system, in this study we only show how the fuzzy XOR function can be constructed and how it can be used to extract edges from grayscale images. One main advantage of our... 

    Random data and key generation evaluation of some commercial tokens and smart cards

    , Article 2014 11th International ISC Conference on Information Security and Cryptology, ISCISC 2014 ; 2014 , p. 49-54 Boorghany, A ; Sarmadi, S. B ; Yousefi, P ; Gorji, P ; Jalili, R ; Sharif University of Technology
    In this paper, we report our evaluation of the strength of random number generator and RSA key-pair generator of some commercially available constrained hardware modules, i.e., tokens and smart cards. That was motivated after recent related attacks to RSA public keys, which are generated by constrained network devices and smart cards, and turned out to be insecure due to low-quality randomness. Those attacks are mostly computing pair-wise GCD between the moduli in public keys, and resulted in breaking several thousands of these keys. Our results show that most of the tested hardware modules behave well. However, some have abnormal or weak random generators which seem to be unsuitable for... 

    Fast architecture for decimal digit multiplication

    , Article Microprocessors and Microsystems ; Volume 39, Issue 4-5 , June–July , 2015 , Pages 296-301 ; 01419331 (ISSN) Fazlali, M ; Valikhani, H ; Timarchi, S ; Tabatabaee Malazi, T ; Sharif University of Technology
    Elsevier  2015
    Abstract BCD digit multiplication module (BDM) is widely used in BCD arithmetic, especially in Decimal Floating-Point (DFP) units. In this paper, we present a new BCD digit multiplication scheme to accelerate this module. Similar to previous articles, our multiplier includes two parts contained binary multiplier and binary to BCD converter. Our contribution towards these modules can successfully overcome the previous BCD digit multipliers. The results indicate 19% hardware acceleration for the proposed multiplier architecture which is comparable to the best previous techniques in UMC 65 nm CMOS standard cells library hardware implementation. Therefore, the proposed BCD digit multiplier is an... 

    Improving hardware Trojan detection using scan chain based ring oscillators

    , Article Microprocessors and Microsystems ; Volume 63 , 2018 , Pages 55-65 ; 01419331 (ISSN) Asadi Kouhanjani, M. R ; Jahangir, A. H ; Sharif University of Technology
    Elsevier B.V  2018
    In recent years, the security of integrated circuits (ICs) has received more attention as usage of ICs made by untrustworthy foundries has increased in safety-critical systems [1]. In this paper, we introduce a novel approach for fingerprinting the delay of functional paths in a sequential circuit that have millions of transistors, like processors. We present a method for inserting Ring Oscillators (ROs) into scan chain for measuring the delay of each functional path inside the chip. Using the proposed method, the payload part of Trojans will be detected according to their size and cell types. Our method can be used by power-based Trojan detection approaches for finding the trigger part of... 

    Hardware Trojan detection and localization based on local detectors

    , Article Turkish Journal of Electrical Engineering and Computer Sciences ; Volume 26, Issue 3 , 2018 , Pages 1403-1416 ; 13000632 (ISSN) Bazzazi, A ; Manzuri Shalmani, M. T ; Hemmatyar, A. M. A ; Sharif University of Technology
    Turkiye Klinikleri Journal of Medical Sciences  2018
    Hardware Trojans are one of the serious threats with detrimental, irreparable effects on the functionality, security, and performance of digital integrated circuits. It is difficult to detect Trojans because of their diversity in size and performance. While the majority of current methods focus on Trojan detection during chip testing, run-time techniques can be employed to gain unique advantages. This paper proposes a method based on the online scalable detection technique, which eliminates the need for a reference chip. Involving local detectors, this technique assesses the variations in the logical values of each node to find out whether there are Trojans. This method excludes time and... 

    Performance evaluation of communication networks for parallel and distributed systems

    , Article Parallel Computing ; Volume 32, Issue 11-12 , 2006 , Pages 775-776 ; 01678191 (ISSN) Sarbazi Azad, H ; Ould Khaoua, M ; Zomaya, A. Y ; Sharif University of Technology

    High-level symbolic simulation using integer equations

    , Article Canadian Conference on Electrical and Computer Engineering; Technology Driving Innovation, 2004, Niagara Falls, 2 May 2004 through 5 May 2004 ; Volume 3 , 2004 , Pages 1241-1244 ; 08407789 (ISSN); 0780382536 (ISBN) Gharehbaghi, A. M ; Hessabi, S ; Eshghi, M. R ; Sharif University of Technology
    Taylor Expansion Diagram (TED) has been recently introduced as a compact and canonical representation for arithmetic functions with finite Taylor series. It can represent Boolean logic interacting with arithmetic functions canonically. One of the main disadvantages of TED is that relations must be bit expanded to be represented in TED. This paper represents a method for high-level symbolic simulation and property checking based on integer equations. Functionality of design is represented in Conditional TED (CTED), which is our enhancement of TED to represent relations without bit expansion. This way, a more compact structure is achieved for high-level designs, containing control path... 

    Fast co-verification of HDL models

    , Article Microelectronic Engineering ; Volume 84, Issue 2 , 2007 , Pages 218-228 ; 01679317 (ISSN) Asadi, G ; Miremadi, S. G ; Ejlali, A ; Sharif University of Technology
    This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks... 

    Evaluation of FPGA Hardware as a New Approach for Accelerating the Numerical Solution of CFD Problems

    , Article IEEE Access ; Volume 5 , 2017 , Pages 9717-9727 ; 21693536 (ISSN) Ebrahimi, A ; Zandsalimy, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    The main purpose of this paper is to investigate the feasibility of using field programmable gate arrays (FPGAs) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the fluid dynamics differential equations. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is a system on a chip FPGA type that integrates both microprocessor and FPGA architectures into a single device. In this paper, typical computational fluid dynamics... 

    Designing best effort networks-on-chip to meet hard latency constraints

    , Article Transactions on Embedded Computing Systems ; Vol. 12, issue 4 , June , 2013 ; ISSN: 15399087 Seiculescu, C ; Rahmati, D ; Murali, S ; Sarbazi-Azad, H ; Benini, L ; Micheli, G. D ; Sharif University of Technology
    Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform... 

    Design and construction of an 8-bit computer, along with the design of its graphical simulator for pedagogical purposes

    , Article 2012 15th International Conference on Interactive Collaborative Learning, ICL 2012, 26 September 2012 through 28 September 2012 ; September , 2012 ; 9781467324274 (ISBN) Ajdari, M ; Tabandeh, M ; Sharif University of Technology
    In an introductory course of computer architecture, it is of high value that students use a simple and special CPU designed for this purpose and also its graphical simulator for better understanding of the computer hardware operation. In this paper, we present Abu-Reiahn, a simple 8-bit processor which we have specifically designed and built as the introduction part of computer architecture course to help students familiarize with hardware and software of a real CPU. Effective use of our computer graphical simulator along with the hardware allow the students to deepen their knowledge of logic circuits and the need for desired timing signals in a CPU to perform specific tasks