Sharif Digital Repository

The ODYSSEY design methodology is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these method calls are implemented in hardware functional units, while others are simply executed by a general-purpose processor. There is a communication overhead because functional units must communicate with each other and with the processor core. In this paper we utilize the custom instructions capability of Nios II processor to enhance the performance of our ASIP. Since these instructions are in the processor itself, there will be no communication overhead for using them. We analyze the performance of the... 

In this paper, different models of gain enhanced amplifier are compared and the most accurate one is chosen. Based on this model, complete symbolic small signal analysis is performed and a design procedure leading to high speed gain boosted amplifier is presented  

A new approach for the design of two-stage Miller-compensated CMOS op amps is presented. The paper studies the basic relations between power consumption, unitygain bandwidth, the biasing region, technology parameters, and the external capacitive load. As a result, simple and efficient design guides are provided to achieve the minimum possible power consumption for the given specifications and for short-channel devices. It is shown that the conventional design procedures do not always result in minimum power op amps. The presented results are also verified by Spectre simulations  

A method to design a tunable low noise amplifier (LNA) for multiband receivers is proposed. This paper also presents a single-ended to differential conversion (S2DC) topology which improves the LNA linearity without degrading its noise performance. Combining input tuning with S2DC in a single stage reduces power consumption of the LNA and decreases effects of supply noise. An LNA has been designed based on the proposed method for 2.3-4.8 GHz in a 0.18 μm CMOS technology. Simulations show an IIP3 of -3.2 dBm, a less than 3.7 dB noise figure (NF), a voltage gain of 24 dB in the whole frequency range. The LNA draws 13.1 mW from a 1.8 V supply. The results indicate that the proposed tuning... 

A single chip UHF-RFID transceiver front-end is presented. The chip was designed according to EPCglobal Class-1 Gen-2 and supports both ETSI and FCC requirements. The receiver front end is capable of rejecting self-jammers as large as 10 dBm with the aid of a feedback loop. The stability and the robustness of the loop and other system requirements are studied. A 30 dBm class-AB power amplifier (PA) with 28% PAE is also integrated on the chip. The pseudo differential architecture of the PA greatly reduces the injection of the signal into the substrate. A simple model is used to estimate the effect of the substrate noise injection by the PA on the receiving circuit modules and design guides... 

The design strategy and efficiency optimization of UHF micro-power rectifiers using a novel diode connected MOS transistor is presented. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduce the threshold voltage and leakage current in compare to conventional diode connected transistors. Using the proposed diode in typical rectifiers makes a significant improvement in output voltage and current therefore the efficiency is increased comparing to the same rectifier architectures using conventional diodes. Also a design procedure for efficiency optimization is presented and a superposition method is used to optimize the performance of multiple output... 

Phase Change Memory (PCM) devices are one of the known promising technologies to take the place of DRAM devices with the aim of overcoming the obstacles of reducing feature size and stopping ever growing amounts of leakage power. In exchange for providing high capacity, high density, and nonvolatility, PCM Multilevel Cells (MLCs) impose high write energy and long latency. Many techniques have been proposed to resolve these side effects. However, read performance issues are usually left behind the great importance of write latency, energy, and lifetime. In this article, we focus on read performance and improve the critical path latency of the main memory system. To this end, we exploit... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity... 

Process variation has already emerged as a major concern in design of multi-processor system on chips (MPSoC). In recent years, there have been several attempts to bring variability awareness into the task scheduling process of embedded MPSoCs to improve performance yield. This study attempts to provide a comparative study of the current variation-aware design-time task and communication scheduling techniques that target embedded MPSoCs. To this end, the authors first use a sign-off variability modelling framework to accurately estimate the frequency distribution of MPSoC components. The task scheduling methods are then compared in terms of both the quality of the final solution and the... 

The objective of this work is to design electrostatic actuators for a CMOS-MEMS nano-newton capacitive force sensor to suppress vertical vibrations disturbances. Electrostatic actuators are selected because the movable part of this force sensor is anchored to the fixed parts. In the first step, we propose a framework for simulation of the force sensor based on finite element method. The proposed model is modified utilizing comparison between the simulation and experimental models to improve the performance of the model. Then, 14 pairs of electrostatic actuators are designed for applying the control algorithm and their pull-in voltage is calculated. In next step, Modal Analysis is applied to... 

Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm... 

Nowadays, leakage energy constitutes up to 80% of total cache energy consumption and tag array is responsible for a considerable fraction of static energy consumption. An approach to reduce static energy consumption is to replace SRAMs by STT-RAMs with near zero leakage power. However, a problem of an STT-RAM cell is its limited write endurance. In spite of previous studies which have targeted the data array, in this study STT-RAMs are used in the L1 tag array. To solve the write endurance problem, this paper proposes an STTRAM/SRAM tag architecture. Considering the spatial locality of memory references, the lower significant bitlines of the tag update more. The SRAM part handles the updates... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

Inter-wire coupling capacitances can lead to crosstalk fault that is strongly dependent on the transition patterns appearing on the wires. These transition patterns can cause mutual influences between adjacent wires of NoCs and as a result threaten the reliability of data transfer seriously. To increase the reliability of NoCs against the crosstalk fault, Forbidden Pattern Free (FPFs) codes are used. To generate FPF codes, numerical systems are among the overhead-efficient mechanisms. The algorithms of numerical systems have direct effect on the amounts of the codec overheads including power consumption, area occupation and performance of NoCs. To find an overhead-efficient numerical system,... 

Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise  

This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- boldsymbol mu ext{m} CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ( n-{ ext {opt}} ), maximum achievable power gain ( G-{P} ), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n ) is offered where dc-power consumption of the circuit ( P-{ ext {dc}} ) is also considered. This formula optimizes G-{P}/P-{ ext {dc}} , and it is preferred over the conventional n-{ ext {opt}} formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB... 

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 μ m CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from... 

This paper presents an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some IPs are provided by trusted and some by untrusted sources. It suffices that a ring-oscillator based sensor is conveniently routed next to a signal that carries secret information (for instance, a cryptographic key), for this information to possibly get leaked. To address this security concern, we apply several different strategies and evaluate them on benchmark circuits from Verilog-to-Routing tool suite. Our experiments show that, for a... 

By Technology improvement, tens or hundreds of IP cores, operating complex functions with different frequencies, are mapped on-chip. This results in heterogeneous Multiprocessor System-on-Chip (MPSoC). The most MPSoC design challenges are due to infrastructure interconnect. Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology, routing and switching schemes have great effects on overall interconnect performance under different synthesis and real life traffic patterns. In this paper, we evaluate Butterfly network with arbitrary extra stages as MPSoC infrastructure. Different routing and...