Sharif Digital Repository

In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-At fault testing  

In this paper a strategy is proposed for compressing the test data while using concurrent hybrid-BIST methodologyfor testing SoCs. In the proposed method, in addition tousing BIST strategy for testing cores with deterministic sequential test patterns in an SoC( Without using scan chains), (ATE) is used for testing cores with deterministic test patterns through Test Access Mechanism (TAM) or functional bus. As will be shown in experimental results, this process compresses hybrid-BIST overall test patterns considerably that affects the overall Test Application Time (TAT) in comparison with pure deterministic, pure pseudo random, and combination of deterministic and pseudo random test patterns  

Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. In our register allocation method, several high-level testability parameters including sequential depth, sequential loop, and controllability/observability are considered. Our experiments show using this register allocation method results in significant improvement in automatic test pattern generation time... 

We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and... 

Due to the growing complexity of today's digital circuits, the speed of fault simulation has become increasingly important. Although critical path tracing (CPT) is faster than conventional methods, it is not fast enough for fault simulation of complex circuits with a large number of faults and tests. Exact stem analysis is the most important obstacle in accelerating the CPT method. The simplification of stem analysis eliminates time-consuming computations and makes the CPT method more parallelizable. An approximate and bit-parallel CPT algorithm is proposed for ultrafast fault simulation for both stuck-at-fault (SAF) and transition delay fault (TDF) models. Time linearity, speedup, and... 

In this paper, jitter due to both capacitive and inductive coupling is studied. Maximum frequency of driving signal on a wire is limited by its input rise time, fall time, pulse width, and the coupling effect from its neighbors. The analytical expressions to estimate the deterministic jitter time due to these effects are presented. The estimation is based on the fastest and slowest approximation of the signal waveform components. Also, we have extracted the eye opening parameters of the eye diagram. The inductance effects significance is shown on eye opening and jitter time. The 45nm technology is used for estimating the horizontal and vertical eye opening and jitter time. The presented... 

This paper introduces a novel scalable pipelined VLSI architecture for a 4×4 64-QAM hard-output multiple-input-multiple-output (MIMO) detector based on K-best lattice decoders. The key contribution is a means of expanding the intermediate nodes of the search tree on-demand, rather than exhaustively, along with three types of distributed sorters operating in a pipelined structure. The proposed architecture has a fixed critical path independent of the constellation size, on-demand expansion scheme, efficient distributed sorters, and is scalable to higher number of antennas. Fabricated in 0.13 μCMOS, it occupies 0.95 μ mm} 2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW... 

The current literature lacks the VLSI realization of hig-horder multiple-input-multiple-output (MIMO) detectors in the complex domain, which finds applications in advanced wireless standards such as WiMAX and Long Term Evolution (LTE) systems. In this paper, a novel modified complex K-Best algorithm and its VLSI implementation for a 4 ×4, 64QAM complex MIMO detector are proposed. The main contributions of this paper are the modified hard-output complex K-Best algorithm as well as its efficient architecture, which is well-suited for a pipelined VLSI implementation. By using an efficient fast multiplier and applying both fine-grain pipelining and coarse-grain pipelining to the architecture of... 

Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are α and β recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing....