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A parameterized graph-based framework for high-level test synthesis

Safari, S ; Sharif University of Technology | 2006

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  1. Type of Document: Article
  2. DOI: 10.1016/j.vlsi.2005.08.004
  3. Publisher: 2006
  4. Abstract:
  5. Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. In our register allocation method, several high-level testability parameters including sequential depth, sequential loop, and controllability/observability are considered. Our experiments show using this register allocation method results in significant improvement in automatic test pattern generation time and fault coverage. © 2005 Elsevier B.V. All rights reserved
  6. Keywords:
  7. Algorithms ; Controllability ; Costs ; Design aids ; Sequential circuits ; Simulated annealing ; Conflict graph ; High-level synthesis for testability ; Register allocation ; Weighted graph coloring ; Integrated circuit testing
  8. Source: Integration, the VLSI Journal ; Volume 39, Issue 4 , 2006 , Pages 363-381 ; 01679260 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/pii/S0167926005000325