Sharif Digital Repository

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch... 

Presents information on global MTTS society education initiatives. © 2000-2012 IEEE  

Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques  

In this paper, different models of gain enhanced amplifier are compared and the most accurate one is chosen. Based on this model, complete symbolic small signal analysis is performed and a design procedure leading to high speed gain boosted amplifier is presented  

In this paper we analyses the energy consumption of well known family of asynchronous circuits and present a new methodology for energy estimation of these circuits at intermediate-level of abstraction. Energy estimation is performed by simulating the intermediate format of the design. The number of Read and Write accesses on the ports of the concurrent processes are counted by analyzing the conditional and computational portion during the simulation which is the base of our estimation methodology. Our proposed power estimation scheme is faster than usual post-synthesis power estimation by an order of 9, while the estimated power resides in a boundary of 11% total imprecision. © 2007 IEEE  

An analytic method for prediction of oscillation amplitude and supply current of differential CMOS oscillators is presented. The validity of this method has been verified by designing an LC CMOS oscillator in a 0.24 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage  

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM  

In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by [9]. After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with... 

A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from... 

In parallel with enhancements in the technology of integrated circuits, transistors are implemented in silicon. Though the price is reduced; design is more complicated, which create the efficiency and power consumption. The reason why modern GDI-based circuit is the focus of attention is that in designing digital circuit, less power is required while more efficiency is obtained. Lowering the complexity of logic circuit can bring about reduction of power consumption, propagation delay and decrease circuit space. GDI-based integrated circuit resembles MOSFET transistors but have fewer transistors and higher performance capability. This study addresses two main areas which are Studying and... 

In this paper, we argue that communication at the speed of light (CaSoL) through on-chip copper interconnects is possible in the near future based on giga-scale integration (GSI) technologies. A three-step algorithm is introduced to design the optimum buffers in such systems. HSPICE simulations show that a 1.3× time of flight (TF) is reachable in 7-nm FinFET technology. It is also shown that such a design is by nature, robust, and immune to process variations and crosstalk noise. © 1963-2012 IEEE  

The spatial Green's function of the open microstrip structure is usually represented by the time-consuming and computationally inefficient spectral integral. This paper introduces a new closed form Green's function for the open microstrip structure by applying the GGF method. Therefore, the numerical integration of the spectral integral can be avoided entirely, leading to a considerable decrease of calculating time. Owing to the remarkable resemblances between the CI and GGF methods, for improvement of approximation especially in large distances, some useful techniques such as extraction of the surface wave poles can be carried out. Even though only an open microstrip structure with one... 

The design of a complex active-RC filter for low-IF Wireless applications is described. Fifth-order complex Butterworth filter is designed using Class-AB operational amplifier architecture. This new structure makes the filter suitable for low power applications with high dynamic range. Simulation results show that the filter provides more than 40 dB image rejection ratio (IIR) and dynamic range of 82dB. The complete filter including on-chip tuning circuit consumes only 4.3mW with 1.8V single supply voltage. © 2007 IEEE  

In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE  

This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW  

In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-At fault testing  

An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first... 

The transformer-feedback (TRFB) interstage bandwidth enhancement technique for broadband multistage amplifiers is presented. Theory of the TRFB bandwidth enhancement and the design conditions for maximum bandwidth, maximally flat gain, and maximally flat group delay are provided. It is shown that the TRFB bandwidth enhancement can provide higher bandwidth compared to the conventional techniques based on reactive impedance matching networks. A three-stage low-noise amplifier (LNA) monolithic microwave integrated circuit with the TRFB between its consecutive stages is designed and implemented in a 0.1-μ m GaAs pHEMT process. The TRFB is realized by coupling between the drain bias lines of... 

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in...