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Graph based fault model definition for bus testing

Karimi, E ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1109/VLSI-SoC.2013.6673246
  3. Publisher: IEEE Computer Society , 2013
  4. Abstract:
  5. In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-At fault testing
  6. Keywords:
  7. Integrated circuit testing ; AMBA bus ; Complemetntary graph ; Fault model ; Primary graph ; SoC ; Buses
  8. Source: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, Istanbul ; October , 2013 , Pages 54-55 ; 23248432 (ISSN) ; 9781479905249 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6673246