Sharif Digital Repository

Networks on Chip1 have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties 2 which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs on to the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs to be... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

Scratch Pad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM into three parts: 1) a part is equipped with Non-Volatile Memory (NVM) which is immune against soft errors, 2) a part is equipped with Error-Correcting Code, and 3) a part is equipped with parity. The proposed mapping algorithm is responsible to distribute the program blocks among the above three parts with regards to their vulnerability... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

The Cauchy-Born (CB) hypothesis has been widely used in multi-scale modeling of crystalline nano-structures. The violation of CB hypothesis in stress space and the transition to plasticity, which is equivalent to the violation of CB hypothesis in strain space, are generally confused and it becomes crucial to differentiate between the two distinct phenomena; the violation of the former usually occurs at high values of stress and at regions where the surface effects are manifest while the violation of the latter occurs at low stresses when the material loses its strength to tolerate the applied loading. In this paper, a novel technique is developed to investigate the validity of CB hypothesis... 

The Cauchy–Born (CB) hypothesis has been widely used in multi-scale modeling of crystalline nano-structures. The violation of CB hypothesis in stress space and the transition to plasticity, which is equivalent to the violation of CB hypothesis in strain space, are generally confused and it becomes crucial to differentiate between the two distinct phenomena; the violation of the former usually occurs at high values of stress and at regions where the surface effects are manifest while the violation of the latter occurs at low stresses when the material loses its strength to tolerate the applied loading. In this paper, a novel technique is developed to investigate the validity of CB hypothesis... 

Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens to hundreds IP cores. Higher scalability (compared to the traditional shared bus and point-to-point interconnects), throughput, and reliability are among the most important advantages of NoCs. Moreover, NoCs can well match current CAD methodologies mainly relying on modular and reusable structures with regularity of structural pattern. However, since NoCs are resource-limited, determining how to distribute application load over limited on-chip resources (e.g. switches, buffers, virtual channels, and wires) in order to improve the metrics of interest and satisfy... 

This paper proposes three ILP-based static thermalaware mapping algorithms for 3D Networks on Chip (NoC) to explore the thermal constraints and their effects on temperature and performance. Through complexity analysis, we show that the first algorithm, an optimal one, is not suitable for 3D NoC. Therefore, we develop two approximation algorithms and analyze their algorithmic complexities to show their proficiency. As the simulation results show, the mapping algorithms that employ direct thermal calculation to minimize the temperature reduce the peak temperature by up to 24% and 22%, for the benchmarks that have the highest communication rate and largest number of tasks, respectively. This... 

Networks-on-Chip (NoCs for short) are known as the most scalable and reliable on-chip communication architectures for multi-core SoCs with tens to hundreds IP cores. Proper mapping the IP cores on NoC tiles (or assigning threads to cores in chip multiprocessors) can reduce end-to-end delay and energy consumption. While almost all previous works on mapping consider higher priority for the application's flows with higher required bandwidth, a mapping strategy, presented in this paper, is introduced that considers multicast communication flows in addition to the normal unicast flows. To this end, multicast and unicast traffic flows are first characterized in terms of some new metrics which are... 

Recent experiments on metals have shown that all of the stress invariants should be involved in the constitutive description of the material in plasticity. In this paper, a plasticity model for metals is defined for isotropic materials, which is a function of the first stress invariant in addition to the second and the third invariants of the deviatoric stress tensor. For this purpose, the Drucker-Prager yield criterion is extended by addition of a new term containing the second and the third deviatoric stress invariants. Furthermore for estimating the cyclic behavior, new terms are incorporated into the Chaboche's hardening evolution equation. These modifications are applied by adding new... 

Recent research studies on ductile fracture of metals have shown that the ductile fracture initiation is significantly affected by the stress state. In this study, the effects of the stress invariants as well as the effect of the reverse loading on ductile fracture are considered. To estimate the reduction of load carrying capacity and ductile fracture initiation, a scalar damage expression is proposed. This scalar damage is a function of the accumulated plastic strain, the first stress invariant and the Lode angle. To incorporate the effect of the reverse loading, the accumulated plastic strain is divided into the tension and compression components and each component has a different weight... 

Networks-on-Chip (NoCs for short) are known as the most scalable and reliable on-chip communication architectures for multi-core SoCs with tens to hundreds IP cores. Proper mapping the IP cores on NoC tiles (or assigning threads to cores in chip multiprocessors) can reduce end-to-end delay and energy consumption. While almost all previous works on mapping consider higher priority for the application's flows with higher required bandwidth, a mapping strategy, presented in this paper, is introduced that considers multicast communication flows in addition to the normal unicast flows. To this end, multicast and unicast traffic flows are first characterized in terms of some new metrics which are... 

In this paper, an Uzawa-type augmented Lagrangian contact formulation is presented for modeling frictional discontinuities in the framework of the X-FEM technique. The kinematically nonlinear contact problem is resolved based on an active set strategy to fulfill the Kuhn-Tucker inequalities in the normal direction of contact. The Coulomb's friction rule is employed to address the stick-slip behavior on the contact interface through a return mapping algorithm in conjunction with a symmetrized (nested) augmented Lagrangian approach. A stabilization algorithm is proposed for the robust imposition of the frictional contact constraints within the proposed augmented Lagrangian framework. Several... 

Long term evolution (LTE)-advanced aims the peak data rates in excess of 3 Gbps for the next generation wireless communication systems. Turbo codes, the specified channel coding scheme in LTE, suffers from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple Maximum a Posteriori (MAP) cores in parallel, resulting in a large area overhead, a big drawback. The scaled Max-log MAP algorithm is a common approach to implement the MAP algorithm due to its efficient architecture with its acceptable performance. Although many works have been reported to reduce the area of the MAP unit, an efficient VLSI... 

SRAM-based scratchpad memories (SPMs) used in embedded systems impose high leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed as NVMs have negligible leakage power. The main problem of utilizing NVMs across the SPM is their limited number of write cycles (endurance). This problem threatens the reliability of NVM-based SPMs. To alleviate the problem of limited endurance in NVM-based SPMs, this paper proposes a method, called overwrite purging through in-execution memory address snooping (OPTIMAS). The main idea behind the proposed method is to control the lifetime of NVM-based SPMs, directly by a hardware unit, outside of the SPM mapping algorithm. This idea... 

Crosstalk faults occurring in wires of Networks on Chip (NoCs) can seriously threaten the reliability of data transfer. One efficient way to tackle crosstalk faults is numeral-based Crosstalk Avoidance Codes (CACs). Numeral-based CACs reduce crosstalk faults by preventing specific transition patterns to occur. One-Lambda Codes (OLCs) are the most efficient types of CACs. However, the codec of OLCs imposes overheads including power consumption, critical path and area occupation to the routers of NoCs. To find overhead-efficient OLCs, this paper proposes an Algorithm for Generating OLC Numeral systems (AGON). AGON provides a tradeoff for designers in selecting overhead-efficient OLCs. Using... 

This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, XOR extraction, and carry-signalmapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted XORs into half/full-adders to make a very fast debugging algorithm. This approach is robust...