Sharif Digital Repository

When multicore processors entered in industry and parallel processing became popular, most challenges have started. Some of the challenges include binding and time sharing of an application with deadline meating constraint. Another important challenge is that, these kinds of processors become more susceptible to transient faults. Among solutions to the mentioned challenges, virtualization which was one of the well known ones becomes applicable again because of some of its advantages such as flexibility, high abstraction and low cost implementation. But this technology has some drawbacks too. It can make system complex and leads to memory and performance overhead. Constructing a reliable... 

Shortest path computation is one the fundamental problems in computer science. Triangulated Irregular Networks (TINs) are used in computational geometry to represent terrians and geometric surfaces. One of the most efficient mothods to solve the shortest path problem on a TIN is reducing it to shortest path problem on a graph. This reduction from continuous space to discrete space results in approximate solutions, but acceptable in real applications. In real applications we still encounter a large graph and using the simple Dijkstra algorithm consumes a lot of times. Memory shortage is another issue. Parallel processing could be a solution in this case. Multicore industry caused a... 

Multi core processors are becoming mainstream in the computation area, wide application of multi core processors in Engineering, Industrial purposes and scientific applications made them popular among users and Manufacturers, cloud computing is a very well known Concept which technically is a Multicore processing environment, most of Businesses, enterprises and engineering works nowadays are getting done by the help of cloud services, hence, to get the best of these multi core cloud computing systems, scheduling of the tasks on the cores and virtual machines(VMs) is necessary, which is the answer to two questions: each task must be assigned to which core(VM)? And What is the order of... 

Data generation rate is far more than the technology scaling rate in a way that there will be a 40x gap between the data generation rate and the technology scaling rate in 2020. On one hand, unlike traditional HPC clusters, processors in data centers are not fully utilized and on the other hand, unlike traditional embedded processors, they are not idle most of the time. Therefore, energy consumption of such processors is an important issue; otherwise dealing with a huge volume of data will be problematic in the near future. In this dissertation, we will show that while first level data cache encounters high miss rate, traditional approaches such as data prefetching, which were efficient for... 

Reducing the size of transistors has dramatically increased the impacts of NBTI, HCI, and EM phenomena in comparison with decade ago. These phenomena are able to have influence on properties of different parts of a chip to make it changed gradually; including threshold voltage of a transistor and electrical conductivity of interconnections. These changes are known as the aging of a transistors that diminish the performance and reliability of a chip. A common reason that plays a significant role in all these phenomena is temperature. The temperature becomes more important when the power density increases per unit area due to decreased size of transistors, which is a trend in multi-core... 

Interactions among proteins and resulted networks of such interactions have a central role in biology. Aligning these networks leads effective information such as finding conserved complexes and evolutionary relationships. The inofrmation provided by global alignment of these networks is more meaningful in comparison to local alignment. In the problem of global alignment, time complexity is one of the most important challenges. Today, multi-core processors are used to solve many time-consuming bioinformatics problems. In this thesis, after reviewing pervious approaches on global alignment of biological networks, we present two novel algorithm for this problem. The first one is designed for... 

By increasing speed gap between microprocessors and off-chip Last Level Cache, Optimization in Last Level Cache makes improvement in system performance. With development of new generation of multi-core processors and sharing LLC between these cores, the so called issue of Memory Wall has caused an incremental effect of LLC on system performance. There are three approaches to use this memory more efficiently:
1. Increasing cache capacity
2. Making cache hierarchical and adding different layers to hierarchy
3. Improvement of replacement algorithms in cache memory
The first approach has not been used in regard with limitation of technology and growth of access time due to... 

Server workloads operate on large volumes of data. As a result, processors executing these workloads encounter frequent L1-D misses. An L1-D miss causes a request packet to be sent to an LLC slice and a response packet to be sent back to the L1-D, which results in high overhead. While prior work targeted response packets, this work focuses on accelerating the request packets through a simple-yet-effective predictor. Upon the occurrence of an L1-D miss, the predictor identifies the LLC slice that will serve the next L1-D miss and a circuit will be set up for the upcoming miss request to accelerate its transmission. When the upcoming miss occurs, the resulting request can use the already... 

Since multi-core processors have become a primary trend in processor development, new scheduling algorithms are needed to minimize power consumption while achieving the desired timeliness guarantees for multi-core real-time embedded systems. Although various power/energy efficient scheduling algorithms have recently been proposed, existing studies may have degraded run-time performance in terms of power/energy efficiency and real-time guarantees when applied to real-time embedded systems with uncertain execution time. Moreover, these algorithms are only provided for a specific set of tasks, while many industrial applications with real-time demands are composed of mixed sets of tasks with a... 

Time constraints are one of the most important concerns in embedded systems. In these systems, to ensure that the system operates correctly in all cases, the worst-case execution time of the system must be less than the deadline. Therefore, reducing worst-case execution time is one of the main design objectives in embedded systems. In addition to time constraints, many embedded systems have energy consumption constraints and hence reducing energy consumption is another main design objective in embedded systems. In this thesis we present two approaches to reduce worst-case execution time as well as an approach to reduce energy consumption while observing time constraints. Our first proposed... 

Due to the technological improvement, decreasing transistor’s size and increasing demand for more processing abilities, designing and implementing multi core processors becomes a hot topic. One of the direct effects of decreasing the size is increasing the rate of power consumption in a unit area. Thus, the generated heat by the processor will be increased. Increasing the temperature could has undesired effects on the other features of the processor such as reliability, efciency, and failure rate. The problems that caused due to the high temperature in the multicore processors is not limited to the maximum temperature, but temperature fluctuations and variation between different parts of the... 

Due to the increasing development of digital systems based on limited energy sources (i.e. battery), energy efficiency has become one of the most important concerns in the design of these systems. The use of multi-core architecture is an effective solution for the problem of reducing energy consumption. Hence using it in digital systems has become more common. In addition, enabling methods for reducing energy consumption on processor, helps in making energy more efficient. DVFS and DPM are the two major methods used for reducing dynamic and static energy consumption of processors. The using of multi-core architecture due to the higher chip density, results the static and dynamic energy... 

Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. For decades, this approach provides desired performance for parallel and multithreaded workloads. On the other hand, rising of utilization wall limits the number of transistors that can be powered on in chip and result in a large region to be dark. So, same as before trend for performance scaling in future multi processor, an appropriate architecture is essential. There are some structures for this era which used specialization approach to cope with the limited power budget. Therefore, in this thesis, we propose a general-purpose platform that provides...