Sharif Digital Repository

High resolution and low power analog to digital converters are used in wireless communication receivers, Sensor Networks and Medical Instrumentations. Reducing power consumption at a high conversion rate is one of the most basic challenges for these converters. Pipelined SAR structure is considered for 40-50 MS/s and 10-12 bits, and is of interest because of consuming low power and using a small area. Besides using Pipelined SAR structure, circuit level and system level modifications are also proposed to decrease the power consumption. The ADC is designed in 0.18µm CMOS technology with 1.2v supply voltage. The results show 4.5mW power consumption, when ENOB is 11.04bit, which is very low... 

High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 40 M sample/s with a power consumption of 20mW for the input level of 1Vp-p and a 1V power supply in 0.13μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized analytically which leads to simple back-envelope formulas to... 

With the rapid development of wireless communication standards, the co-existence of multiple standards in a single chip becomes inevitable. It is also fueling interest in analog to digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions with adaptive power consumption. Employing such ADCs rather than using multiple individually power-optimized ADCs results in a great reduction of silicon area. Hence, a reconfigurable ADC can reduce time to market, and save costs.
This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The... 

High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to... 

High speed data converter are very often used in telecommunication systems. Since these systems are increasingly used in mobile foem reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate 200MS/s with a power consumption of 35 mW for the input level of 1Vp-p and a 1.8V power supply in 0.18um CMOS technology.
To reach these goals, a number of low power techniqes are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a... 

During recent years the main concern of analog designers is to get the most use of Computer Aided Design (CAD) tools for design procedures.Thus the main purpose of this thesis is to introduce a very fast and precise CAD tool for the design of pipelined analog to digital converters (ADC). This is accomplished by utilizing some simulation and optimization based CAD tools at the same time. In the optimization part, the conventional numerical methods are replaced with the proposed analytical approaches. Also, anew algorithm is used in the simulation part, which makes the monte-carlo simulation to be faster compared to the conventional cases. To verify the accuracy of CAD tool performance, a...