Search for: technology-roadmaps
Method Developing of National Technology Roadmap for Heavy Turbofan Engine Industry based on Conceptual design, M.Sc. Thesis Sharif University of Technology ; Mazaheri, Karim
In this thesis, a method developed for producing technology roadmap to identify technologies needed in design, construction and testing of turbofan engines. In the first phase and in scoping step, 10 years’ time horizon is determined. Then project organization and the role required are intended and after that the second phase that is technology roadmap formation is begun. Market identification, product identification by key success factors forms and experts are steps of this phase and determination of three generations of engine are results of product identification step. After that, the technology identification step is begun but simultaneously the technology mapping drawing steps for...
Developing a model for integrating decisions in technology roadmapping by fuzzy PROMETHEE, Article Journal of Intelligent and Fuzzy Systems ; Volume 26, Issue 2 , 2014 , Pages 625-645 ; ISSN: 10641246 ; Daneshmand Mehr, M ; Arasti, M. R ; Sharif University of Technology
Roadmapping, a tool of strategic planning, visualize where and how an organization will be in the future. Visualization of strategic programs assists people in the organization to understand the strategy which is a key for implementing strategy successfully. A generic roadmap is included of three main layers such as; market, product and technology. Decision making in each layer are done separately because of the nature of each layer. Therefore, decisions in roadmapping can be done with different tools. Whiles, decisions in each layer of the roadmap cannot be done without considering the upper or lower layer decisions. In this study we propose Fuzzy PROMETHEE method for integrating decisions...
Multi-hop communications on wireless network-on-chip using optimized phased-array antennas, Article Computers and Electrical Engineering ; Volume 39, Issue 7 , 2013 , Pages 2068-2085 ; 00457906 (ISSN) ; Tabandeh, M ; Kaffash, S ; Raahemi, B ; Sharif University of Technology
Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC); The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the International Technology Roadmap for Semiconductors annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the...
Temperature-Dependent Comparison between Delay of CNT and Copper Interconnects, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 24, Issue 2 , 2016 , Pages 803-807 ; 10638210 (ISSN) ; Sarvari, R ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
The performance of gigascale integration chips improves by cryogenic technologies such as subambient cooling. In these conditions, interconnects may perform at temperatures as low as 50 K. However, the local temperature of interconnects could easily be as high as 600 K at high-temperature chips. In this brief, we investigated the impact of temperature on delay of local, intermediate, and global interconnects of International Technology Roadmap for Semiconductors Node 2024. This is done for different values of interconnect width and length, nanotube diameter, and percentage of metallic carbon nanotubes (CNTs) in a grown bundle. Results are compared with those of copper counterpart. We showed...
An opto-electrical NoC with traffic flow prediction in chip multiprocessors, Article Proceedings - 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014 ; 2014 , Pages 440-443 ; Arjomand, M ; Sarbazi Azad, H ; Sharif University of Technology
Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology to integrate numerous IP blocks on a single chip. The achievable performance of adopting NoCs is constrained by the performance limitation mainly imposed by the metal wires that are the physical realization of communication channels. According to the International Technology Roadmap for Semiconductors (ITRS) report, new interconnect paradigms providing huge bandwidth is in need for future products. The current wired channels have limited bandwidth, and consequently, they limit the performance enhancements that NoC architectures can provide. Optical interconnects are capable of achieving better performance via...
Technology planning system for the Iranian petroleum industry: lessons learned from sanctions, Article Technological Forecasting and Social Change ; Volume 122 , 2017 , Pages 170-178 ; 00401625 (ISSN) ; Ghazinoory, S ; Arasti, M ; Fassihi, S. F ; Sharif University of Technology
Iran's petroleum industry is facing challenges including maturity of hydrocarbon fields, growing population of the nation that demands additional revenues from petroleum exports, and international economic sanctions that have limited access to technology sources. Restrictions from international technology providers have led managers of the industry enterprises to try to develop their needed technologies inside the country. The Ministry of Petroleum has supervised this and as a result, a technology planning systems has been developed and implemented since 2009. In this paper, an overview of the Iranian petroleum industry is provided from a technology planning perspective. The focus has been...
An optimized phased-array antenna for intra-chip communications, Article LAPC 2011 - 2011 Loughborough Antennas and Propagation Conference, 14 November 2011 through 15 November 2011 ; November , 2011 , Page(s): 1 - 4 ; 9781457710155 (ISBN) ; Tabandeh, M ; Kaffash, S ; Sharif University of Technology
The continued migration to smaller nanometer geometries brought fundamental limits to traditional on-chip hard wires performance. According to the International Technology Roadmap for Semiconductor (ITRS), feature size shrinking leads an increase in the operating frequency of RFCMOS devices. Thus, new interconnect methodologies such as radio frequency (RF) wireless can be employed on future chips projected for intra-chip wireless data communications. The size of Si integrated antenna in these frequencies will be several millimetres and the antenna length will be decrease by frequency increasing. In this paper, we have proposed an optimum radiation pattern achieved by a phased array (PA)...
Effect of number of faults on NoC power and performance, Article 13th International Conference on Parallel and Distributed Systems, ICPADS, Hsinchu, 5 December 2007 through 7 December 2007 ; Volume 1 , December , 2007 ; 15219097 (ISSN); 9781424418909 (ISBN) ; Nadi, M ; Manzuri Shalmani, M. T ; Rahmati, D ; Sharif University of Technology
According to International Technology Roadmap for Semiconductors (ITRS), before the end of this decade, we will be entering the era of a billion transistors on a single chip. The major threat toward the achievement of billion transistor on a chip is poor scalability of current interconnect infrastructure. With the advent of "Network on Chip (NoC)" various characters and methodologies of traditional networks were hardly considered on-chip. Failure, Power and Area are the major concepts that should be considered when migrating from traditional interconnection networks to NoCs. In this paper we study the effects of faulty links and nodes on power and performance of mesh based NoC, Also several...