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Effect of number of faults on NoC power and performance

Ghadiry, M. H ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/ICPADS.2007.4447766
  3. Publisher: 2007
  4. Abstract:
  5. According to International Technology Roadmap for Semiconductors (ITRS), before the end of this decade, we will be entering the era of a billion transistors on a single chip. The major threat toward the achievement of billion transistor on a chip is poor scalability of current interconnect infrastructure. With the advent of "Network on Chip (NoC)" various characters and methodologies of traditional networks were hardly considered on-chip. Failure, Power and Area are the major concepts that should be considered when migrating from traditional interconnection networks to NoCs. In this paper we study the effects of faulty links and nodes on power and performance of mesh based NoC, Also several routing algorithms have been implemented and simulated using a cycle accurate VHDL model of NoC1. © 2007 IEEE
  6. Keywords:
  7. Electric network topology ; Industrial management ; Transistors ; Cycle-accurate ; Fault ; Faulty links ; Interconnection network ; Interconnection networks ; International conferences ; International technology Roadmap for Semiconductors ; Mesh-based NoC ; Network on chip ; On chips ; Parallel and distributed systems ; Performance ; Power ; Routing algorithm ; Single chips ; Transistor on a chip ; Routing algorithms
  8. Source: 13th International Conference on Parallel and Distributed Systems, ICPADS, Hsinchu, 5 December 2007 through 7 December 2007 ; Volume 1 , December , 2007 ; 15219097 (ISSN); 9781424418909 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4447766