Search for: total-power-consumption
0.005 seconds

    Low-power technique for dynamic comparators

    , Article Electronics Letters ; Volume 52, Issue 7 , 2016 , Pages 509-511 ; 00135194 (ISSN) Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Institution of Engineering and Technology 
    A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-ampli-fication phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%  

    Scheduling to minimize gaps and power consumption

    , Article Journal of Scheduling ; Volume 16, Issue 2 , April , 2013 , Pages 151-160 ; 10946136 (ISSN) Demaine, E. D ; Ghodsi, M ; Hajiaghayi, M ; Sayedi Roshkhar, A. S ; Zadimoghaddam, M ; Sharif University of Technology
    This paper considers scheduling tasks while minimizing the power consumption of one or more processors, each of which can go to sleep at a fixed cost α. There are two natural versions of this problem, both considered extensively in recent work: minimize the total power consumption (including computation time), or minimize the number of "gaps" in execution. For both versions in a multiprocessor system, we develop a polynomial-time algorithm based on sophisticated dynamic programming. In a generalization of the power-saving problem, where each task can execute in any of a specified set of time intervals, we develop a (1+23α) -approximation, and show that dependence on α is necessary. In... 

    Towards the optimal tracking interval management for target tracking wireless sensor networks

    , Article ATC 2009 - Proceedings of the 2009 International Conference on Advanced Technologies for Communications, 12 October 2009 through 14 October 2009 ; 2009 , Pages 161-166 ; 9781424451395 (ISBN) Jamali Rad, H ; Abolhassani, B ; Abdizadeh, M ; Sharif University of Technology
    We consider the minimization of power consumption in target tracking wireless sensor networks (WSNs) using dynamic modification of tracking interval. In this context, we first analyze the performance of such networks, using a quantitative mathematical analysis. Then we calculate an upper bound for the achievable improvement in total power consumption, when using an adaptive time interval modification algorithm for tracking moving objects with acceleration. Towards this optimum functionality, we propose a novel adaptive algorithm (AHC) to adapt the tracking interval such that it minimizes power consumption while keeping an acceptable accuracy. Simulation results show that using the proposed... 

    Data center power reduction by heuristic variation-aware server placement and chassis consolidation

    , Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 150-155 ; 9781467314824 (ISBN) Pahlavan, A ; Momtazpour, M ; Goudarzi, M ; Sharif University of Technology
    The growth in number of data centers and its power consumption costs in recent years, along with ever increasing process variation in nanometer technologies emphasizes the need to incorporate variation-aware power reduction strategies in early design stages. Moreover, since the power characteristics of identically manufactured servers vary in the presence of process variation, their position in the data center should be optimally determined. In this paper, we introduce two heuristic variation-aware server placement algorithm based on power characteristic of servers and heat recirculation model of data center. In the next step, we utilize an Integer Linear Programming (ILP) based... 

    An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators

    , Article Proceedings of the International Symposium on Low Power Electronics and Design, 22 July 2015 through 24 July 2015 ; Volume 2015-September , July , 2015 , Pages 249-254 ; 15334678 (ISSN) ; 9781467380096 (ISBN) Sadrosadati, M ; Mirhosseini, A ; Aghilinasab, H ; Sarbazi Azad, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to... 

    SRAM leakage reduction by row/column redundancy under random within-die delay variation

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 18, Issue 12 , 2010 , Pages 1660-1671 ; 10638210 (ISSN) Goudarzi, M ; Ishihara, T ; Sharif University of Technology
    Share of leakage in total power consumption of static RAM (SRAM) memories is increasing with technology scaling. Reverse body biasing increases threshold voltage (Vth), which exponentially reduces subthreshold leakage, but it increases SRAM access delay. Traditionally, when all cells of an SRAM block used to have almost the same delay, within-die variations are increasingly widening the delay distribution of cells even within a single SRAM block, and hence, most of these cells are substantially faster than the delay set for the entire block. Consequently, after the reverse body biasing and the resulting delay rise, only a small number of cells violate the original delay of the SRAM block; we... 

    A distributed task migration scheme for mesh-based chip-multiprocessors

    , Article Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings, 20 October 2011 through 22 October 2011 ; Oct , 2011 , Pages 24-29 ; 9780769545646 (ISBN) Yaghoubi, H ; Modarresi, M ; Sarbazi Azad, H ; Sharif University of Technology
    A task migration scheme for homogeneous chip multiprocessors (CMP) is presented in this paper. The proposed migration mechanism focuses on the communication sub-system and aims to reduce the total power consumption and latency of the network-on-chip (NoC). In this work, starting from an initial mapping, the tasks migrate to new cores in such a way that the distance between the end-point nodes of high-volume communication flows is reduced. Finding the new place for a task is done in a distributed manner by applying an iterative local search that relies on the local information of each task about its communication demand. The task migration procedure also includes a pre-migration step that... 

    A high-speed method of dynamic comparators for sar analog to digital converters

    , Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-Amplifier stage) is limited to V dd=2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above V dd=2. As a result, during the comparison the second stage of the comparator (latch) is activated stronger compared to the conventional comparator. To prove the benefits of the proposed comparator, the proposed and the other circuits are simulated in the equal budget of power and offset. Simulation results prove that the proposed comparator is faster... 

    Peak-power-aware energy management for periodic real-time applications

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 39, Issue 4 , 2020 , Pages 779-788 Ansari, M ; Yeganeh Khaksar, A ; Safari, S ; Ejlali, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Two main objectives in designing real-time embedded systems are high reliability and low power consumption. Hardware replication (e.g., standby-sparing) can provide high reliability while keeping the power consumption under control. In this paper, we consider a standby-sparing system where the main tasks on primary cores are scheduled by our proposed peak-power-aware earliest-deadline-first policy while the backup tasks on spare cores are scheduled by our proposed peak-power-aware earliest-deadline-late policy to meet the chip thermal design power (TDP) constraint. These policies provide the best opportunity to shift the task executions as much as possible to minimize execution overlaps... 

    An N-Path filter design methodology with harmonic rejection, power reduction, foldback elimination, and spectrum shaping

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 67, Issue 12 , 2020 , Pages 4494-4506 Karami, P ; Banaeikashani, A ; Behmanesh, B ; Atarodi, S. M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is... 

    ReMap: reliability management of peak-power-aware real-time embedded systems through task replication

    , Article IEEE Transactions on Emerging Topics in Computing ; August , 2020 , Pages: 1-1 Yeganeh Khaksar, A ; Ansari, M ; Ejlali, A ; Sharif University of Technology
    IEEE Computer Society  2020
    Increasing power densities in future technology nodes is a crucial issue in multicore platforms. As the number of cores increases in them, power budget constraints may prevent powering all cores simultaneously at full performance level. Therefore, chip manufacturers introduce a power budget constraint as Thermal Design Power (TDP) for chips. Meanwhile, multicore platforms are suitable for implementation of fault-tolerance techniques to achieve high reliability. Task Replication is a known technique to tolerate transient faults. However, careless task replication may lead to significant peak power consumption. In this paper, we consider the problem of achieving a given reliability target... 

    A compact mixer and DAC for implementation of a direct conversion OQPSK transmitter

    , Article 2007 IEEE Region 10 Conference, TENCON 2007, Taipei, 30 October 2007 through 2 November 2007 ; 2007 ; 1424412722 (ISBN); 9781424412723 (ISBN) Chahardori, M ; Mehrmanesh, S ; Zamanlooy, B ; Atarodi, M ; Sharif University of Technology
    A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power...