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A high-speed method of dynamic comparators for sar analog to digital converters

Khorami, A ; Sharif University of Technology | 2017

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  1. Type of Document: Article
  2. DOI: 10.1109/MWSCAS.2016.7869961
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2017
  4. Abstract:
  5. A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-Amplifier stage) is limited to V dd=2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above V dd=2. As a result, during the comparison the second stage of the comparator (latch) is activated stronger compared to the conventional comparator. To prove the benefits of the proposed comparator, the proposed and the other circuits are simulated in the equal budget of power and offset. Simulation results prove that the proposed comparator is faster by a factor of two. The comparator delay, dynamic offset , and power consumption (at 500 MHz) are 255 ps, 2.6 mV , and 420 uW respectively. Moreover, the maximum input common mode of the proposed circuit is 94%V dd at 500MHz which is better than the conventional method (68%V dd). © 2016 IEEE
  6. Keywords:
  7. ADC ; Dynamic comparator ; High-speed ; Low-power ; Twostage comparator ; Amplifiers (electronic) ; Analog to digital conversion ; Budget control ; Comparator circuits ; Electric power utilization ; Analog to digital converters ; Conventional methods ; Dynamic comparators ; High Speed ; Low Power ; Output voltages ; Total power consumption ; Voltage fluctuations ; Comparators (optical)
  8. Source: 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/7869961