Sharif Digital Repository

Information integrity in cache memories is a fundamental requirement for dependable computing. As caches comprise much of a CPU chip area and transistor counts, they are reasonable targets for single and multiple transient faults. This paper presents: 1) a fault detection scheme for tag arrays of cache memories and 2) an architectural cache to improve dependability as well as performance. In this architecture, cache space is divided into sets of different sizes and different tag lengths. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. The results show that error detection... 

This paper presents an analysis of the effects and propagation of faults in the open-core 32-bit OpenRISC 1200 microprocessor. The analysis is based on a total of 13,000 transient faults injected into 65 parts of the CPU module in the OpenRISC 1200 core described at the RTL model. A comparison of the effects of faults on the various parts of the CPU including the pipeline's registers, the CPU component such as the register file, the control unit, and the ALU, and the data and address buses is done. It is shown that about 30%, 40% and 27% of injected faults terminated in address, data, and control errors respectively. About 28% of all injected faults resulted in failures. © 2008 IEEE  

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer... 

Nowadays, distributed embedded systems are employed in many safety-critical applications such as X-by-Wire. These systems are composed of several nodes interconnected by a network. Studies show that a transient fault in the communication controller of a network node can lead to errors in the fault site node (called original errors) and/or in the neighbor nodes (called follow-up errors). The communication controller of a network node can be halted due to an error, which may be a follow-up error. In this situation, a follow-up error leads to halt the correct operation of a fault-free controller while the fault site node, i.e. the faulty controller, still continues its operation. In this paper,... 

This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques. © 2009 IEEE  

In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error correction technique is compatible with all existing error detection techniques which are proposed for the CSA adder. The synthesized results show that applying this novel error correction technique to a CSA with error detection technique results in up to 18.4%, 3.1% and 14.9%, increase in power consumption, delay and area respectively. © 2009 IEEE  

To the best knowledge of us, survivability for WSN has never been studied considering failure affects on network. We perceive the network survivability as a composite measure consisting of both network failure duration and failure impact on the network. In this paper we will study network survivability in unstably state: in this state, network is affected by the failures that occur temporarily and instantly also may occur several times. In other words, the main characteristics of these failures are their frequency and being temporary. In this paper we will propose a survivability model for network in unstable state that is based on network availability. This availability model, presents... 

This paper presents an experimental evaluation of transient effects on SRAM-based FPGAs. A total of 9000 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD). The results show that nearly 60 percent of faults cause system failures and about 58 percent of the faults lead to corruption of the configuration data of the FPGA chip. © 2005 IEEE  

This paper introduces an analytical method for approximating the performance of a soft real-time system modeled by a single-server queue. The service discipline in the queue is earliest-deadline-first (EDF), which is an optimal scheduling policy. Real-time jobs with exponentially distributed deadlines arrive according to a Poisson process. All jobs have deadlines until the end of service and are served non-preemptively. Occurrences of transient faults in the server are also taken into account. The important performance measure to calculate is the loss probability due to deadline misses and/or transient faults. The system is approximated by a Markovian model in the long run. A key parameter,... 

In this paper, we present a scan-chain-based multiple error recovery technique for triple modular redundancy (TMR) systems (SMERTMR). The proposed technique reuses scan-chain flip-flops fabricated for testability purposes to detect and correct faulty modules in the presence of single or multiple transient faults. In the proposed technique, the manifested errors are detected at the modules' outputs, while the latent faults are detected by comparing the internal states of the TMR modules. Upon detection of any mismatch, the faulty modules are located and the state of a fault-free module is copied into the faulty modules. In case of detecting a permanent fault, the system is degraded to a... 

This paper presents a novel approach for evaluating the reliability of protective systems taking into account its components reliability. In this paper, a previously proposed extended model is used for a directional over- current scheme. In the extended model, the impacts of individual protective components are taken into account. An optimum routine test schedule is determined for each protective component as a separate unit. A comparison is made to show that the proposed approach has excellence over conventional routine test inspections. Impacts of factors such as circuit breaker inadvertent opening, required time for performing routine test inspections, human mistakes and self-checking and... 

This paper presents a novel approach for evaluating the reliability of protective systems taking into account its components reliability. In this paper, a previously proposed extended model is used for Directional Overcurrent scheme. In the extended model, the impacts of individual protective components are taken into account. An optimum routine test schedule is determined for each protective component as a separate unit. A comparison is made to show that the proposed approach has excellence over conventional routine test inspections. Impacts of factors such as circuit breaker inadvertent opening, required time for performing routine test inspections, human mistakes and self-checking and... 

This paper presents a centralized fault detection algorithm for wireless sensor networks. Faulty sensor nodes are identified based on comparisons between neighboring nodes and own central node and dissemination of the decision made at each node. RNS system is used to tolerate transient faults in sensing and communication. In this system, arithmetic operations act on residues - reminder of dividing original number in several definite modules - in parallel. Consequently computations on these residues which are smaller than the original number are performed, so speed up arithmetic and decreased power consumption is achieved. ©2009 IEEE  

Nowadays, communication protocols are used in safety-critical automotive applications. In these applications, fault tolerance is a main requirement and the existence of single points of failure is a serious threat to system failures. Among the communication protocols, FlexRay is expected to become the communication backbone for future automotive systems. In this paper, we identify single points of failure in the FlexRay protocol by injecting a total of 135,600 single-bit transient faults into all accessible registers of the FlexRay communication controller. The results showed that about 1.2% of all injected faults caused the controller to freeze immediately. Based on these results and... 

Stalling of residential air conditioners (RACs) following a transient fault can delay the voltage recovery ranging from 3 to 20 seconds. This phenomenon is referred to as fault-induced delayed voltage recovery (FIDVR). Several aggregated RAC models have been presented to replicate the actual FIDVR events. However, they usually have two main drawbacks as: i) considering independent stalling voltage and stalling time for all RACs, ii) resulting in only two ultimate modes; either 100% stalled or 100% normal running. This paper amends the abovementioned shortcomings by proposing a simple and effective performance-based RAC model. The proposed model utilizes a simple explicit relation between the... 

With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of... 

The increasing rate of transient faults necessitates the use of on-chip fault-tolerant techniques in embedded microprocessors. Performance overhead is a challenging problem in on-chip fault-tolerant techniques used in the random logic of the embedded microprocessors. This paper presents a signature-based error detection and roll-back recovery technique for the control logic with much lower performance overhead as compared to many previous techniques. The low performance overhead is achieved by eliminating the fault masking overhead cycles in the previous techniques. The performance overhead is analytically studied, and the analytical results recommend at which fault rate the use of the... 

Given the importance of reducing energy consumption and the challenge of heat generation in classic CMOS circuits, adiabatic circuits are believed as an appropriate alternative. Most of the adiabatic circuit families come with a dual-rail structure, which provides them with an inherent hardware redundancy. Although this redundancy could be used for improving their reliability, no studies have been previously conducted to exploit this feature. In this regard, in this paper, we show that by exploiting the inherent hardware redundancy in adiabatic circuits, their reliability could be improved, while imposing a relatively low amount of energy overhead. Subsequently, with utilizing the outcome... 

While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is...