Sharif Digital Repository

Network-on-Chips (NoCs) consume a significant portion of multiprocessors' total power. Dynamic Voltage Scaling (DVS) which can reduce both static and dynamic power consumption is widely applied to NoCs. However, prior DVS schemes usually impose significant performance overhead to NoCs as NoCs need to work with lower clock frequencies when the supply voltage is scaled down. In this chapter, we propose a novel DVS scheme for NoCs with no performance overhead. We reduce power consumption when there is few Virtual Channels (VCs) that have active allocation requests at each cycle compared to the total number of available VCs. To enable multiple latencies with different slack times, we propose a... 

Network-on-Chips (NoCs) consume a significant portion of multiprocessors' total power. Dynamic Voltage Scaling (DVS) which can reduce both static and dynamic power consumption is widely applied to NoCs. However, prior DVS schemes usually impose significant performance overhead to NoCs as NoCs need to work with lower clock frequencies when the supply voltage is scaled down. In this chapter, we propose a novel DVS scheme for NoCs with no performance overhead. We reduce power consumption when there is few Virtual Channels (VCs) that have active allocation requests at each cycle compared to the total number of available VCs. To enable multiple latencies with different slack times, we propose a... 

Graphics Processing Units (GPUS) are widely used as the accelerator of choice for applications with massively data-parallel tasks. However, recent studies show that GPUS suffer heavily from resource underutilization, which, combined with their large static power consumption, imposes a significant power overhead. One of the most power-hungry components of a GPU-the execution units-frequently experience idleness when (1) an underutilized warp is issued to the execution units, leading to partial lane idleness, and (2) there is no active warp to be issued for the execution due to warp stalls (e.g., waiting for memory access and synchronization). Although large in total, the idle time of... 

This paper introduces a stochastic dynamic power management policy for soft real-time systems. Such a system comprises a single processor with the capability of dynamic voltage scaling (DVS). The policy uses DVS to consume less power in the processor while satisfying some performance constraints. The idea is based on a Markovian model of the system, which presents an analytical technique for tuning the system parameters and evaluating the effectiveness of the policy. Real-time jobs arrive according to a Poisson process and have exponentially distributed service times and relative deadlines. The power management policy is designed to reduce the long-run power consumption of the system while... 

Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techniques based on time-redundancy. In this paper we analyze the usage of information redundancy in DVS-enabled systems with the aim of improving both the system tolerance to transient faults as well as the energy consumption. We demonstrate through a case study that it is possible to achieve both higher fault-tolerance and less energy using a combination of information and time redundancy when compared with using time redundancy alone. This even holds despite the impact of the information redundancy hardware overhead... 

Due to non-linear factors such as the rate capacity and the recovery effect, the shape of the battery discharge curve plays a significant role in the overall lifetime of the batteries. Accordingly, this paper proposes a simple heuristic battery-aware speed scheduling policy for periodic and non-periodic real-time tasks in Dynamic Voltage Scaling (DVS) systems with non-negligible leakage/static power. A set of comprehensive analysis has been conducted to compare the battery efficiency of the proposed policies with an optimal solution, which could be derived via the Calculus of Variations (CoV). These evaluations have taken into account both periodic and non-periodic tasks in DVS-based... 

In modern multicore mixed-criticality (MC) systems, a rise in peak power consumption due to parallel execution of tasks with maximum frequency, specially in the overload situation, may lead to thermal issues, which may affect the reliability and timeliness of MC systems. Therefore, managing peak power consumption has become imperative in multicore MC systems. In this regard, we propose an online peak power and thermal management heuristic for multicore MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and per-cluster dynamic voltage and frequency scaling (DVFS). Specifically, our approach examines... 

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM  

Recently, the tradeoff between low energy consumption and high fault-tolerance has attracted a lot of attention as a key issue in the design of real-time systems. Dynamic Voltage Scaling (DVS) is commonly employed as one of the most effective low energy techniques for real-time systems. It has been observed that the use of feedback-based methods can improve the effectiveness of DVS-enabled systems. In this paper, we have investigated reducing the energy consumption of fault-tolerant hard real-time systems using the feedback control theory. Our proposed method makes the system capable of selecting the proper frequency and voltage settings in order to reduce the energy consumption, while... 

The interaction between fault tolerance and energy consumption is an interesting avenue in the realm of designing embedded systems. In this paper, a scheme for reducing energy consumption in conventional standby-sparing systems is introduced. In the proposed method, the primary unit exploits dynamic voltage scaling (DVS) and dynamic power management (DPM) is employed for the spare unit. The framework which is used in the primary unit is composed of a feedback system to follow up workload along with a three-layer yet light-weight energy manager which guarantees hard real-time constraints of the system. Moreover, an optimal approach (but not practical) as a margin for the minimum energy... 

Low energy consumption and fault tolerance are often key objectives in the design of real-time embedded systems. However, these objectives are at odds, and there is a trade-off between them. Real-time systems usually use system level energy reduction methods, i.e., dynamic voltage scaling (DVS) and dynamic power management (DPM). Also hard real-time systems often use replication to achieve fault tolerance. In this paper, we investigate the impact of system level energy reduction methods on both the reliability and energy consumption of hard real-time systems which use replication for fault tolerance. In this analysis, we have considered four various existing energy management methods: 1)... 

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to... 

Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling... 

Embedded systems are usually energy constrained. Moreover, in these systems, increased productivity and reduced time to market are essential for product success. To design complex embedded systems while reducing the development time and cost, there is a great tendency to use commercial off-the-shelf ("COTS") devices. At system level, dynamic voltage and frequency scaling (DVFS) is one of the most effective techniques for energy reduction. Nonetheless, many widely used COTS processors either do not have DVFS or apply DVFS only to processor cores. In this paper, an easy-to-implement COTS-based evaluation platform for low-energy embedded systems is presented. To achieve energy saving, DVFS is... 

Recently, the tradeoff between low energy consumption and high fault-tolerance has attracted a lot of attention as a key issue in the design of real-time embedded systems. Dynamic Voltage Scaling (DVS) is known as one of the most effective low energy techniques for real-time systems. It has been observed that the use of control-theoretic methods can improve the effectiveness of DVS-enabled systems. In this paper, we have investigated reducing the energy consumption of fault-tolerant hard real-time systems using feedback control theory. Our proposed feedback-based DVS method makes the system capable of selecting the proper frequency and voltage settings in order to reduce the energy... 

Checkpointing with rollback recovery is a well-established technique to tolerate transient faults. However, it incurs significant time and energy overheads, which go wasted in fault-free execution states and may not even be feasible in hard real-time systems. This paper presents a low-overhead two-state checkpointing (TsCp) scheme for fault-tolerant hard real-time systems. It differentiates between the fault-free and faulty execution states and leverages two types of checkpoint intervals for these two different states. The first type is nonuniform intervals that are used while no fault has occurred. These intervals are determined based on postponing checkpoint insertions in fault-free... 

CPU-GPU heterogeneous systems are emerging as architectures of choice for high-performance energy-efficient computing. Designing on-chip interconnects for such systems is challenging; CPUs typically benefit greatly from optimizations that reduce latency, but rarely saturate bandwidth or queueing resources. In contrast, GPUs generate intense traffic that produces local congestion, harming CPU performance. Congestion-optimized interconnects can mitigate this problem through larger virtual and physical channel resources. However, when there is little traffic, such networks become suboptimal due to higher unloaded packet latencies and critical path delays.We argue for a reconfigurable network...