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BiNoCHS: bimodal network-on-chip for CPU-GPU heterogeneous systems

Mirhosseini, A ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1145/3130218.3130222
  3. Abstract:
  4. CPU-GPU heterogeneous systems are emerging as architectures of choice for high-performance energy-efficient computing. Designing on-chip interconnects for such systems is challenging; CPUs typically benefit greatly from optimizations that reduce latency, but rarely saturate bandwidth or queueing resources. In contrast, GPUs generate intense traffic that produces local congestion, harming CPU performance. Congestion-optimized interconnects can mitigate this problem through larger virtual and physical channel resources. However, when there is little traffic, such networks become suboptimal due to higher unloaded packet latencies and critical path delays.We argue for a reconfigurable network that can activate additional channels under high load/congestion and shut them off when the network is unloaded. However, these additional resources consume more power, making it difficult to statically provision a power budget for the network. We introduce BiNoCHS, a reconfigurable voltage-scalable on-chip network for heterogeneous systems. Under CPU-dominated low-traffic conditions, BiNoCHS operates at nominal-voltage and high clock frequency with a topology optimized for low hop count, maximizing CPU performance. Under high-traffic GPU and mixed workloads, it transitions to a near-threshold mode, activating additional routers/channels and non-minimal adaptive routing to resolve congestion. Our evaluation shows that BiNoCHS improves CPU/GPU performance by 57% / 34% over a latency-optimized network under congested conditions, while improving CPU performance by 28% over high-bandwidth design in unloaded conditions. © 2017 Association for Computing Machinery
  5. Keywords:
  6. Bimodal network-on-chip ; Bandwidth ; Bins ; Bismuth compounds ; Budget control ; Energy efficiency ; Graphics processing unit ; Integrated circuit design ; Network-on-chip ; Program processors ; Routers ; Servers ; Traffic congestion ; Voltage scaling ; Energy efficient computing ; Heterogeneous systems ; Non-minimal adaptive routing ; On-chip interconnects ; Packet latencies ; Physical channels ; Reconfigurable network ; Traffic conditions ; Integrated circuit interconnects
  7. Source: 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, 19 October 2017 through 20 October 2017 ; 2017 ; 9781450349840 (ISBN)
  8. URL: https://dl.acm.org/citation.cfm?id=3130222