Design and Simulation of Phase Detector and Other Digital Circuits of an All Digital Frequency Synthesizer to Decrease Phase Noise and Lock Time

Please enable javascript in your browser.

Ensafdaran, Masoud | 2009

892 Viewed

Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 39217 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Atarodi, Mojtaba
Abstract:
In this thesis, An All Digital Frequency Synthesizer for use in RF applications is designed in 180nm CMOS. Different blocks such as Phase detector, Loop filter and Loop counter is designed. Finally, an All Digital Frequency Synthesizer is modeled using this circuits and an Digitally controlled oscillator model and is designed for GSM. In this thesis a new method is proposed to noise shape the quantization noise of the time to digital converter. The Time to Digital Converter has 7mW power consumption for 0ns to 1ns input range. Using this noise shaping method, quantization noise is reduced about 20dB. Also, limit cycle related spurs is reduced significantly using first order and second order noise shaping. To decrease the noise shaping problems in Flip Flops, the flip flops are replaced with sense amplifiers. The sense amplifier is designed to have metastability region on 5ps. To decrease lock time, Gear shifting method is used. At first, the synthesizer is locked with a wide bandwidth and then reduced to final band width. To simulate the different loop parameters, the synthesizer is modeled in time, phase and frequency domain.
Keywords:
Phase Noise ; Flip Flop ; All Digital Frequency Synthesizer ; Time to Digital Converter ; Sense Amplifier ; Lock Time

No TOC