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- Type of Document: M.Sc. Thesis
- Language: English
- Document No: 39672 (52)
- University: Sharif University of Technology, International Campus, Kish Island
- Department: Science and Engineering
- Advisor(s): Sarbazi Azad, Hamid
- Abstract:
- The increasing complexity of integrated circuits drives the research of new on chip interconnection architectures. Network On Chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Different routing algorithms have been proposed for NoCs such as XY deterministic algorithm, and WF (West First), NL (North Last) and NF (Negative First) as partially adaptive algorithms. OE (Odd Even) is not based on adding virtual channels to network topologies. Unlike previous methods, which rely on prohibiting certain turns in order to achieve deadlock freedom, this algorithm restricts the locations where some types of turns can be taken. Another algorithm is DYAD-Smart routing for Networks on Chips which combines the advantages of both deterministic and adaptive routing schemes. This routing technique judiciously switches between deterministic and adaptive routing based on the networks congestion conditions. In this project XY, WF, NF and OE algorithms are simulated using XMulator package to evaluate their performance and energy consumption in mesh NoCs. We compare the performance and energy consumption of the above mentioned routing algorithms under different working conditions set in different simulation scenarios
- Keywords:
- Performance Evaluation ; Routing Algorithm ; Network-on-Chip (NOC)
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