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Architecture of Reconfigurable Optical Network-on-Chip

Falahati, Hajar | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 42259 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hesabi, Shahin
  7. Abstract:
  8. According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with reconfigurbility. The goal of this architecture is to check how we can improve the parameters of an optical network based on characteristics of distributed traffic on network on chip. To achieve this goal, it is necessary to change the topology and select links and routers based on application. In order to evaluate the proposed architecture, we first introduce an optical network simulator to implement our proposed architecture at behavioral level, and then compare it with electrical network on chip, as well as optical networks on chip without reconfigurability in terms of power consumption and delay
  9. Keywords:
  10. Optical Transfer ; Network-on-Chip (NOC) ; Reconfiguration

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