Sharif Digital Repository

Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of... 

According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with... 

In recent years, GPUs are becoming an ideal candidate for processing a variety of high performance applications. By relying on thousands concurrent threads in applications and the computational power of large numbers of computing units; GPGPUs have provided high performance and throughput. To achieve the potential computational power of GPGPUs in broader kinds of applications, we need to apply some modifications in their architecture. In the baseline architecture, the maximum part of chip area is devoted to SIMT cores which their communication is handled through an interconnection network and a slow off-chip memory. Recent research shows that out of many types of miss events the last level... 

ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
To address these challenges, we propose a new... 

The importance of power consumption in high performance multiprocessors, combined with power reduction capability of on-chip optical interconnects, offers optical network-on-chip (ONoC) as a new technology solution which can deliver considerably higher bandwidth and lower latencies with significantly lower power dissipation than an interconnection network based only on electronic signaling. An on-chip network should be able to support multicast communications efficiently whether it is an optical or electrical network. On the other hand, multicast communications in optical networks-on-chip has been implemented using shared bus which is not scalable. Moreover, most of optical on-chip... 

In recent years, GPUs are becoming ideal candidates for processing a variety of high performance applications. By relying on thousands of concurrent threads in applications and the computational power of large numbers of computing units, GPGPUs have provided high efficiency and throughput. To achieve the potential computational power of GPGPUs in broader types of applications, we need to apply some modifications. By understanding the features and properties of applications, we can execute them in a more proper way on GPUs. Therefore, considering applications’ behavior, we define 5 different categories for them. Every category has special definitions, and we change the configuration of GPU... 

The downscaling of feature size and higher process variation in COMS nano-technology are anticipated to introduce higher manufacturing anomalies. On the other hand, designs are getting more complicated due to more innovative applications where they need higher numbers of transistors. Because of these issues, integrated circuits manufacturing has become more complicated than before. Complexity in manufacturing process increases the probability of the defects in chips. This phenomenon reduces the fabrication yield. Conventional methods like fault tolerant techniques, defect tolerant techniques and redundancy are not separately good enough for improving manufacturing yield. On the other hand,... 

According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though... 

With the widespread use of mobile applications, multimedia and telecommunications, speed of execution has become important. The computation-intensive portions of applications, i.e., loops, devote a significant percentage of their implementation time. Thus, in this thesis, a new method is introduced which greatly increases the execution speed of the loops. Loops are often implemented on coarse-grained reconfiguration architecture (CGRAs) for acceleration, which is a promising architecture with high performance and high power efficiency in comparison to FPGA. In this regard, to reduce the execution time of two-level nested loops, if there are several innermost loops, first, we fuse them, then... 

Nowadays integrated circuits are extremely vulnerable to hardware trojans (HT). Hardware trojans can be injected into the ICs in design or fabricate phase, and damage system’s functionality or security. In this thesis, we first describe hardware trojan definition, classification and types of HTs, negative effects, detection ways and analysis of them. Then we propose a new solution in order to solve the negative points of previous methods  

With the advent in technology and shrinking the transistor size down to nano scale, static power may become the dominant power component in Networks-on-Chip (NoCs). Power-gating is an efficient technique to reduce the static power of under-utilized resources in different types of circuits. For NoC, routers are promising candidates for power gating, since they present high idle time. However, routers in a NoC are not usually idle for long consecutive cycles due to distribution of resources in NoC and its communication-based nature, even in low network utilizations. Therefore, power-gating loses its efficiency due to performance and power overheads of the packets that encounter powered-off... 

Access to global memory is one of the bottlenecks in performance and energy in GPUs. Graphical processors uses multi-thread in streaming multiprocessors to reduce memory access latency. However, due to the high number of concurrent memory requests, the memory bandwidth of low level memorties and the interconnection network are quickly saturated. Recent research suggests that adjacent thread blocks share a significant amount of data blocks. If the adjacent thread blocks are assigned to specific streaming multiprocessor, shared data block can be rused by these thread blocks. However the thread block scheduler assigns adjacent thread blocks to different streaming multiprocessors that increase... 

Shrinking the dimensions of transistors in recent fabrication technologies has led to an increase in the aging rate of chips, as the most important challenge in reliability of new processors. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effect of transistor shrinkage. These two effects decrease the switching speed of transistors by increasing its threshold voltage over time. Threshold voltage shift causes timing violation in combinational parts of circuit and decreases the robustness of sequential parts against soft errors. Between different units of a processor, Arithmetic and Logic Unit (ALU) is one of the most susceptible units... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects reliability of the chips is modifications or additions with malicious intention,known as Hardware Trojans, which are easily applicable during design and manufacturing phase of chips. There has been an increasing fraud in chip-set manufacturing. Hardware Trojans may leak confidential information outside the chip, to the attacker, may alter the function of circuit, or completely fail a system. Hence search for new... 

With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects relability of the chips is modifications or additions with malicious intension, known as Harware Trojans, which are easily applicable during design and manufacturing phase of chip. This study intends to introduce a model based on the scan chain, a method is provided for intellectual property protection. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require... 

Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different... 

Although cloud porcessors have lots of benefits, they have brought new challenges for designers; one of these issues, is information leakage through Timing Channel Attack in shared hardware resources. Among these shared resources, main memory controller is less understood. Also applying timing channel protection technquies to shared memory controller, in comparison with other parts such as NoC, caches, etc, can impose high performance overhead to system throughput. Temporal Partitioning (TP) is the baseline secure scheduling algorithm that was proposed for cope with timing channel attack in shared memory controller; but beside this protection, TP compels high performance degradation. In this... 

As the number of processing cores on a single chip continues to grow, the need for a high band width, low power communication structure, will be the most important requirements of next generation chip multiprocessors. Today, a major part of power consumption in multi core architectures belongs to interconnects. Due to these facts, reducing consuming power, as well as supporting high performance, is concerned in these architectures. The concept of “network-on-chip” emerged to improve the performance of CMPs. But now a day, considering the circumstances of power budges, it’s incapable of presenting new strategies to decrease consuming power and delay. However, optical interconnects have the... 

As the number of processing cores on a single chip continues to grow, the need for a high bandwidth, low power communication structure, will be the most important requirement of the next generation chip multiprocessors. Today, a major part of power consumption in multicore architectures belongs to interconnects. Due to these facts, reducing power consumption, as well as supporting high performance, is of major concern in these architectures. Optical interconnects have the potential to replace electrical wires to solve the bottleneck of communications in integrated circuits. Various routers and architectures with different points of view, have been recently designed considering existing... 

Integrating functionalities of different-criticality levels on a shared computing platform known as Mixed-Criticality Systems (MCSs) has been noticed recently in research and industrial designs. Due to the battery-operated nature of some MCSs and different reliability requirement for tasks, joint energy and reliability management is crucial in these systems. Another important issue in these systems which is rarely addressed in previous works is tolerating permanent faults. In this thesis, we propose two comprehensive schemes: MC-4S and MC-2S which guarantee to tolerate permanent faults and maintaining the system reliability with respect to the transient faults. In addition, guaranteeing the...