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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 48806 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Hesabi, Shahin
- Abstract:
- With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects relability of the chips is modifications or additions with malicious intension, known as Harware Trojans, which are easily applicable during design and manufacturing phase of chip. This study intends to introduce a model based on the scan chain, a method is provided for intellectual property protection. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require permanent secret key storage in the FPGA. In addition, they cannot provide a commercially popular pay-per-device licensing solution. We want to propose a novel IP protection mechanism to restrict IP’s execution only on specifid FPGA devices in order to efficiently protect IPs from being cloned, copied, or used with unauthorized integration. This mechanism can also enforce the pay-per-device licensing, which enables the system developers to purchase IPs from the core vendors at the low price based on usage instead of paying the expensive unlimited IP license fees.In our mechanism, FPGA vendors embed into each enrolled FPGA device with a Physical Unclonable Function (PUF) customized for FPGAs; IP vendors embed augmented finite-state-machine (FSM) into the original IPs such that the FSM can be activated by the PUF responses from the FPGA device. We analyze the security vulnerabilities of our PUF-FSM-IBS binding method. We implement three 64-bit delay-based PUFs on FPGAs with low overhead. The PUF responses are 49.3% and 49.8% unique and reliable against environment changes. The average power overhead is only 5%
- Keywords:
- Intellectual Property ; Error Correction Codes ; Scan Chain ; Hardware Secunity ; Counterfeit Chip ; Physical Unclonable Function (PUF)
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