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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 42308 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Sarbazi Azad, Hamid
- Abstract:
- On-chip communication infrastructure in chip multiprocessors with large number of processing cores has to be scalable, consumes low power, and provides high bandwidth for hundrededs or even thousands of processing cores. In this project, to this end, the applicability of wireless network technology for on-chip communications in systems with hundreds or thousands of processing elements is investigated. We have combined wired networks (for communication between elements that are close) and wireless networks (for transmition of high volume data flows between cores that are far from each other); so different data flows achive the required bandwidth and point to point delay is reduced. Also, a good tradeoff between performance and power consumption is provided. Hence, we pursuit the following goals by introducing such architecture: 1) The architecture suitably scales with ever increasing number of on-chip cores wich gurantees minumin number of hop counts between any source and destination without using long wires as the number of on-chip cores is increasing. 2) The proposed architecture is simple and has low power consumption and silicon area overhead. Using well-stuctured simulators, hierarchical wireless NoC architectures have been evaluated and simulation results are compared with common on-chip communication infrastrucures (such as wired mesh NoCs). Appropriate models for wirless communication Network behavior and send/recive antennas are emulated in the simulation infrastuctre
- Keywords:
- Network-on-Chip (NOC) ; On-Chip Multiprocessor ; Wireless Communication
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