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10-Bit 500-MS/s Pipelined Analog to Digital Converter

Noormohammadi Khyarak, Mehdi | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43172 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Hajsadeghi, Khosrow
  7. Abstract:
  8. High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to increase the speed of system is used timeinterleaving.also, all non idealities of this method is analyzed .for reducing more power of ADC is used the opamp sharing and for eliminating the nonidealities of this method is proposed the using of two pair input opamps. The simple and high speed S/H is proposed . Next the desired design criteria were obtained by adjusting the parameters through try and error. The final design is a 10 bit analog to digital converter with a power consumption of 39 mw and SNDR = 52.4 dB for the input rate of Fin = 2.6 MHz , ENOB = 8.4 , INL < 1.1 LSB and DNL < 0.6 LSB
  9. Keywords:
  10. Analog to Digital Converter ; Pipeline Converter ; Sample and Hold Circuit ; Time Interleaved Converter ; Opamp Sharing

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