Design of a Fault Tolerant SPARC Based Micro Processor On FPGA

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Hosseini, Morteza | 2012

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 43216 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Rashidian, Bijan; Vosoughi Vahdat, Bijan
Abstract:
In this thesis, LEON Processor was chosen for its compatible architecture that can be implemented on a wide range of FPGAs. The final designed processor is aimed to conquer soft and hard errors that occur due to cosmic radiations in SRAM cells of an FPGA. The system can finally resist all single SEUs that happen in flip flops and all 4 random errors that take place in each register of the register file. All the flip flops and latches are protected using a TMR scheme. The information redundancy in the regiester file to overcome all 4 random errors is 168% and the errors are corrected by means of a mechanesim that is masked from the processor core. In cache memory, each 32 bit data is protected by 4 parity bits that provide detection of a high portion of MBU errors. The mean time to failure (MTTF) calculations of the register file of the designed processor show that if the register file -by using special instruction- is scrubbed every other 48 hours, the probability of system crash reaches to zero in a very harsh environment
Keywords:
Upgrading ; Field Programmable Gate Array (FPGA) ; Register File ; Fault Tolerance ; LEON3 Processor ; Quasi-Cyclic Self Orthogonal Code

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