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RT-Level Test Pattern Generation with Horner Expansion Model

Mirzaei, Mohammad | 2012

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 44370 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Tabandeh, Mahmoud; Navabi, Zainalabedin
  7. Abstract:
  8. Increasing in size and complexity of digital designs has made manufacturing process more complex and enforces more complexity in verification of designs. This makes it essential to address critical verification issues at the early stages of design cycle. Such a complicated designs needs to be tested for fabrication faults as well as functional faults. Several attempts have been made to raise the quality of testing methods with automatic test pattern generation (ATPG) and design for testability (DFT) methods in logic and lower levels. Although these techniques try to increase the testability of a circuit considerably, but there are always some overheads in area, power and performance. Therefore a suitable formal model is required to define fault models and develop test pattern generation techniques at behavioral level of abstraction or even higher. This proposal proposes a high level test generation method which considers the control part as well as data path of an RTL circuit as a set of polynomial functions to generate behavioral test patterns from faulty behavior instead of comparing the faulty and fault-free circuits based on a hybrid Boolean-word canonical representation called Horner Expansion Diagram (HED). Since this set of polynomial functions express primary outputs and next states with respect to primary inputs and present states, it is not necessary to perform justification/propagation phase which leads to a minimum number of backtracks. It improves fault coverage and reduces test generation time over logic-level techniques. We assess then the effectiveness of high-level test generation with a simple gate-level ATPG algorithm. Experimental results show robustness and reliability of our method compared to other contemporary approaches in terms of fault coverage and CPU time
  9. Keywords:
  10. Fault-Detection Coverage ; Sequential Circuit Test ; Horner Expansion Diagram (HED) ; Polynomial Model ; High-Level Test Generation ; Automatic Test Pattern Generation (ATPG)

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