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System Level Communication Testing Considering Functionality

Karimi, Elmira | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44887 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Tabandeh, Mahmoud; Navabi, Zainalabedin
  7. Abstract:
  8. Due to the development of electronics, technology has entered new levels of integration on a single chip, called the System-on-Chip (SoC) design. Currently a SoC may contain various Intellectual Property (IP) cores with different interface protocols. For typical SoC communication, designers implement numerous standards such as Avalon from Altera and AMBA from ARM. These standards have different topologies with their own properties and are suitable for specific applications, But the challengeable problem is testing interconnects between cores. In testing process, important elements of a bus that should be tested are interconnections between cores (wires), multiplexers, arbiters, decoders, and etc. Up to now many methods have been developed for testing the buses. Some of them are at lower level of design, but some other methods are proposed at higher level of. These researches have been independently make some efforts on bus testing. By testing at low level all details of circuit under test will be considered. Thus we can reach high fault coverage but the test procedure is length full and even takes illogical time. On the other hand, Testing at high level is more simple and fast, but in the high level model, many details have been eliminated. Thus it may drop fault coverage. We present a method that collects both advantages of testing from lower level to higher level of abstraction. This goal is achieved by testing the bus step by step named hierarchical functional testing (start-small method). For testing a bus, we should test interconnections and components in the following manner: Wires that include data buses, address buses, control buses, and other available interconnections between two modules and combinational components like decoders and multiplexers, Sequential bus components like arbiters, wrappers, bridges and etc. In our hierarchical functional method we use different methods for testing each part. In the first step, wires and combinational components will be tested. In this part we use special test patterns that are suitable for our methodology. After that, sequential components will be tested. For doing so, we present a high level fault model which has been motivated by a deep study of state machines of bus components, is capable of modeling complex components without losing simplicity. At the end we combined these two steps and present a global scenario for test data generation to test the all parts of bus. Using AMBA-AHB as the experimental result, the proposed scenario shows efficiency in comparison with corresponding stuck-at fault testing
  9. Keywords:
  10. Testability ; System-on-Chip ; AMBA Bus ; Topology Graph ; Fault Model ; State Graph

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