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Through Silicon Via (TSV) to Transistor Noise Coupling Characterization

Amiri, Sajjad | 2014

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 46227 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sarvari, Reza
  7. Abstract:
  8. Due to the physical limitations of the conventional 2D ICs at Giga-Scale Integration, modern technologies have been emerged. Among them, through silicon via (TSV) - based 3D ICs have been used to continue Moore’s law in the interconnect era. In these systems, dies are stacked at z-direction after wafer thinning. Electrical connections between stacked dies are done by TSVs. One important advantage of 3D integration technology is their ability to stack heterogeneous systems with different technologies on a single chip. This will not only increase interconnect density but also will reduce the delay and power consumption. However, nowadays, fabrication and optimum design of TSVs are still big challenges of these 3D structures.
    In my research, I have focused on the noise coupling issues of TSV. Since TSV crosses through silicon substrate, designing TSV and replacing transistor without considering noise coupling will degrade the performance of adjacent circuits. We proposed a compact physical model for noise coupling between TSV and active device in both low doped substrate and epi substrate, based on the image techniques. Then, the model is verified by accurate numerical simulations with Silvaco. We proposed several noise mitigation techniques. At the end of this thesis, the effect of TSV signal on the stability of SRAM is expresse
  9. Keywords:
  10. Three Dimentional Chip ; Compact Method ; Through Silicon Vias (TSV) ; Substrate Noise ; Noise Mitigating

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