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Reducing Power of On-chip Networks by Exploiting Latency Asymmetry of Router’s Pipeline Stages

Sadrosadati, Mohammad | 2014

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 46537 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. NOCs contribute to a large portion of a many-core SOC power consumption. A significant fraction of the mentioned power consumption is due to the buffers, crossbar and the links. Thus, in this thesis, a new method would be introduced which reduces the power consumption of the NOCs in large scale. This method utilizes the latency asymmetry of router pipeline stages for dynamic power reduction and uses different voltage swings for buffers, links and the crossbar in order to decrease the dynamic power consumption while maintaining the performance. Moreover, since the static power consumption has gained a noticeable importance in recent years, a method for degrading this power component is also devised in this thesis. This is done by concentrating on the VCs for maintaining the network throughput in high traffic loads. The VCs are idle for a large portion of runtime in low traffic loads and hence, can be power-gated so as to reduce static energy consumption. By the use of our policy, the VCs would be turned back on when needed and traffic would be controlled. Since the NOCs are the biggest bottleneck in a CMP system, there has been a lot of research works on reducing the overheads of their power reduction. By simultaneous using of our methods, the power consumption of the NOCs would be lowered by 40% while the performance degradation is negligible
  9. Keywords:
  10. Network-on-Chip (NOC) ; Dynamic Power Consumption ; Virtual Channel ; Static Power ; Reduced Voltage Swing ; Router Pipeline ; Power Gating

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