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Using task migration to improve non-contiguous processor allocation in NoC-based CMPs

Modarressi, M ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1016/j.sysarc.2013.03.011
  3. Abstract:
  4. In this paper, a processor allocation mechanism for NoC-based chip multiprocessors is presented. Processor allocation is a well-known problem in parallel computer systems and aims to allocate the processing nodes of a multiprocessor to different tasks of an input application at run time. The proposed mechanism targets optimizing the on-chip communication power/latency and relies on two procedures: processor allocation and task migration. Allocation is done by a fast heuristic algorithm to allocate the free processors to the tasks of an incoming application when a new application begins execution. The task-migration algorithm is activated when some application completes execution and frees up the allocated resources. Task migration uses the recently deallocated processors and tries to rearrange the current tasks in order to find a better mapping for them. The proposed method can also capture the dynamic traffic pattern of the network and perform task migration based on the current communication demands of the tasks. Consequently, task migration adapts the task mapping to the current network status. We adopt a non-contiguous processor allocation strategy in which the tasks of the input application are allowed to be mapped onto disjoint regions (groups of processors) of the network. We then use virtual point-to-point circuits, a state-of-the-art fast on-chip connection designed for network-on-chips, to virtually connect the disjoint regions and make the communication latency/power closer to the values offered by contiguous allocation schemes. The experimental results show considerable improvement over existing allocation mechanisms
  5. Keywords:
  6. Non-contiguous allocation ; Task migration ; Network on chip ; Non-contiguous allocation ; Performance ; Power ; Processor allocation ; Communication ; Heuristic algorithms ; Multiprocessing systems ; Routers ; VLSI circuits ; Microprocessor chips
  7. Source: Journal of Systems Architecture ; Vol. 59, issue. 7 , 2013 , pp. 468-481 ; ISSN: 13837621
  8. URL: http://www.sciencedirect.com/science/article/pii/S1383762113000350