Power Reduction in GPUs through Intra-Warp Instruction Execution Reordering

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Aghilinasab, Homa | 2015

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 47381 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Sarbazi Azad, Hamid
Abstract:
As technology shrinks, the static power consumption is getting worse. Moreover, considering high usage of General-Purpose Graphics Processing Units (GPGPU), reducing the static power of GPGPUs is becoming an important issue. Execution units in GPGPUs are one of the most power hungry units that play an essential role in total power consumption of GPGPUs. On the other hand power gating is a promising method to reduce static power consumption. In this project, we propose a novel method to implement power-gating method for execution units with the negligible performance and power overheads. We utilize out of order execution in intra warp to keep the power-gated resources in off state more than break-even time. We implement our method in GPGPU-Sim and evaluate it under different metrics. The method is compared to the state-of–the-art architecture for implementing power-gating method in execution units. By the use of our proposal, we manage to reduce the static power consumption about 60% and improve the performance about 9%. The main reason for our improving in GPGPU performance is reduction in L1 cache miss rate by using our new warp scheduler
Keywords:
Static Power ; THREADS ; Power Reduction ; Power Gating ; General Purpose Graphic Processing Units (GPGPU) ; Warp Scheduling

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