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Reduced memory requirement in hardware implementation of SVM classifiers

Esmaeeli, S ; Sharif University of Technology | 2012

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  1. Type of Document: Article
  2. DOI: 10.1109/IranianCEE.2012.6292320
  3. Publisher: 2012
  4. Abstract:
  5. Support Vector Machine (SVM) is a powerful machine-learning tool for pattern recognition, decision making and classification. SVM classifiers outperform other classification technologies in many applications. In this paper, two implementations of SVM classifiers are presented using Logarithmic Number System. In the basic classifier all operations (multiplication, addition and ...) are performed using logarithmic numbers. In the logarithmic domain, multiplication and division can be simply treated as addition or subtraction respectively. The main disadvantage of LNS is the large memory requirement for high precision addition and subtraction. In the improved classifier, multiplication operation is performed using logarithmic numbers, but addition and subtraction operations are performed with linear fixed point numbers. In this research a lookup table and a shifter are used to convert LNS numbers to fixed point numbers. The required memory of the improved classifier is 197 times less than the required memory of the basic system without any degradation of the SVM classification accuracy
  6. Keywords:
  7. Basic systems ; Classification technology ; Fixed points ; Hardware implementations ; High precision ; Logarithmic domain ; Logarithmic number system ; Machine-learning ; Memory requirements ; Multiplication operations ; Reduced memory requirements ; SVM classification ; SVM classifiers ; Classifiers ; Electrical engineering ; Hardware ; Number theory ; Numbering systems ; Pattern recognition ; Support vector machines
  8. Source: ICEE 2012 - 20th Iranian Conference on Electrical Engineering, 15 May 2012 through 17 May 2012 ; May , 2012 , Pages 46-50 ; 9781467311489 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6292320