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A Power-efficient Architecture for SRAM-based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

Ebrahimi, Zahra | 2016

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48834 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Asadi, Hossein
  7. Abstract:
  8. Significant increase of static power with downscaling of transistor feature size and threshold voltage has lead to the end of Dennard scaling. This obstacle has put a Power Wall to further integration of CMOS technology in Field Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is to apply power gating to the inactive fractions of a single die, referred to as Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs) which suffer from poor logic utilization, and subsequently, limiting the benefits of power gating techniques. This thesis proposes a heterogeneous Power-Efficient Architecture for FPGAs (PEAF) based on composition of Reconfigurable Hard Logics (RHLs) and a small-input LUT. In the proposed architecture, the unused RHLs and/or LUTs can be selectively turned off within each logic block by employing a reconfigurable power controller (RPC). By mapping the majority of logic functions to simple-design and small RHLs, PEAF is able to significantly improve both static and dynamic power without degrading the performance. Experimental results over a comprehensive set of benchmarks (MCNC, IWLS’05, and VTR) demonstrate that PEAF reduces the total static power and Power-Delay-Product (PDP), on average, by 24.5% and 21.7%, respectively, as compared with baseline 4-LUT architecture. This is while the total performance is also improved by 1.8%. PEAF increases total area by 18.9%, however, it still occupies 22.1% less area footprint than the 6-LUT architecture with 31.5% improvement in PDP
  9. Keywords:
  10. Field Programmable Gate Array (FPGA) ; Static Power ; Look Up Table (LUT) ; Dark Silicon ; Versatile Placement and Routing (VPR)Tools ; Logic Block ; Hard Logic

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