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A low-latency QRD-RLS architecture for high-throughput adaptive applications

Alizadeh, M. S ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSII.2016.2530169
  3. Publisher: Institute of Electrical and Electronics Engineers Inc
  4. Abstract:
  5. A novel architecture for QR decomposition-based recursive least squares is presented. It offers low latency for applications where the channel equalization and adaptive filtering are mandatory. This approach reduces the computations by rewriting the equations in a manner that lets intense hardware resource sharing by reusing similar values in different computations. Moreover, precision range conversion allows for combining complex operations such as root square and division with minimum effect on the overall quantization error. Hence, an efficient lookup table-based solution has highly enhanced the performance of the design by 2.7 times with respect to the previous works
  6. Keywords:
  7. Equalizer ; FPGA ; QR decomposition (QRD) ; Recursive least squares (RLS) ; Adaptive filtering ; Equalizers ; Field programmable gate arrays (FPGA) ; Reconfigurable hardware ; Table lookup ; Adaptive application ; Channel equalization ; Complex operations ; Hardware resources ; Novel architecture ; Adaptive filters
  8. Source: IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 63, Issue 7 , 2016 , Pages 708-712 ; 15497747 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/7407319